Specifications

AHB Monitor

4.3.29 AHBMONCtrlReg

The AHB Monitor disables all the event counters at reset, but enables the Debug output.

For normal device operation the information produced by the AHB Monitor is not

required. AHBMONCtrlReg was included to enable or disable the AHB monitor

module. The Track DBGACK bit was included to provide method of discounting bus

activity caused by the processor operating in debug mode. It only affects the counters

associated with the ARM-D and ARM-I layers, and the CtTotalCyclesNonDebug

counter.

4.3.30 CtTotalCycles

This register contains the total count of AHB bus cycles since the last hardware reset.

The counter cannot be reset and wraps at the upper boundary.

4.3.31 CtTotalCyclesEn

This register contains the total count of AHB Monitor, event counter enabled, AHB bus

cycles since the last hardware or software reset. The count is disabled by default and is

be controlled through AHBMONCtrlReg[1], and reset through the AHBMONRstCtrs.

4.3.32 CtTotalCyclesNonDebug

The CtTotalCyclesNonDebug counter was included to provide a duration count that can

be used in association to the ARM-D and ARM-I layers when the track DBGACK bit

is set in the AHBMONCtrlReg.

This register contains the total count of AHB bus cycles since the last hardware or

software reset, with the event counter enabled while DBGACK is asserted LOW and

AHBMONCtrlReg[2] is asserted HIGH. The count is disabled by default and is be

controlled through AHBMONCtrlReg[1], and reset through the AHBMONRstCtrs.

Table 4-2 AHBMONCtrlReg

Bits Name Type Function

31:3 - - Reserved, read undefined, must be written as zeros

2Track

DBGACK

Read/write When set, it disables ARM x counters when DBGACK is

asserted. Default value at reset is 0.

1 Counter Enable Read/write Enables all event counters. Default value at reset is 0.

0 Debug Enable Read/write Enables the debug output. Default value at reset is 1.