Specifications

AHB Monitor

4.3.22 CtGxiRd

The MBX GXI performs a read transfer completely disjoint from the address cycle.

Transfer requests are acknowledged in the address cycle with the GAREADY signal,

and transfers are completed in subsequent cycles, which are acknowledged by the

GDREADY signal. The MBX initiates a read transfer request by driving GWRITE

LOW and GTRANS HIGH.

This register contains the total count of completed read transfers that have occurred on

the MBX GXI Bus. This register does not contain the total number of accepted transfer

requests. The count is disabled by default and can be controlled through the

AHBMONCtrlReg, and reset through the AHBMONRstCtrs.

4.3.23 CtGxiWrAddrWait

The MBX GXI performs a write transfer in the same cycle as the address cycle, which

can be stalled by taking the GAREADY signal LOW. The MBX initiates a write

transfer request by driving GWRITE and GTRANS HIGH.

This register contains the total count of stalled write transfers that have occurred on the

MBX GXI bus. The count is disabled by default and can be controlled through the

AHBMONCtrlReg, and reset through the AHBMONRstCtrs.

4.3.24 CtGxiRd<layer>Wait

The MBX GXI performs a read transfer completely disjoint from the address cycle.

Transfer requests are acknowledged in the address cycle with the GAREADY signal,

and transfers can be stalled by driving the GDREADY signal LOW. The MBX initiates

a read transfer request by driving GWRITE LOW and GTRANS HIGH.

This description is valid for the following registers:

•

CtGxiRdAddrWait

•

CtGxiRdDataWait.

These registers contain the total count of wait cycles suffered by read transfers that have

occurred on the MBX GXI bus. The count is disabled by default and can be controlled

through the AHBMONCtrlReg, and reset through the AHBMONRstCtrs.