Specifications

AHB Monitor
4-36 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
4.3.20 <layer>WaitThreshold register
The eight WaitThresholdHit registers are associated with a specific AHB layer:
•
ArmdWaitThreshold
• ArmiWaitThreshold
• Dma0WaitThreshold
• Dma1WaitThreshold
• ClcdWaitThreshold
• GxiRdAWaitThreshold
• GxiRdDWaitThreshold
• GxiWrAWaitThreshold.
4.3.21 CtGxiWr
The MBX GXI performs a write transfer in the same cycle as the address cycle, which
is acknowledged by the GAREADY signal. The MBX initiates a write transfer request
by driving GWRITE and GTRANS HIGH.
This register contains the total count of completed write transfers that have occurred on
the MBX GXI Bus. The count is disabled by default. It can be controlled through
AHBMONCtrlReg and reset through AHBMONRstCtrs.
Table 4-1 <layer>WaitThreshold
Bits Name Type Function
[31:4] - - Reserved, read undefined, must be written to with
zeros.
[3:0] <layer>WaitThreshold Read/write Contains the threshold for the maximum number
of stall cycles that may occur on the associated
AHB layer before the associated threshold
violation counter is incremented The default
threshold value is 0.