Specifications

AHB Monitor
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-35
reset through the AHBMONRstCtrs. The counters associated with the ARM D and
ARM I layers are also controlled by the DBGACK in relation to configuration, see
AHBMONCtrlReg on page 4-39.
4.3.18 Ct<layer>WaitNonSeqBus
The NONSEQ bus wait count registers are associated with a specific AHB layer:
•
CtArmdWaitNonSeqBus
• CtArmiWaitNonSeqBus
• CtDma0WaitNonSeqBus
• CtDma1WaitNonSeqBus
• CtClcdWaitNonSeqBus
• CtExpWaitNonSeqBus.
These registers contain the total count of wait states incurred on the first transfer of a
burst caused by the bus infrastructure on the associated AHB layer. The count is
disabled by default. It can be controlled through AHBMONCtrlReg and reset through
AHBMONRstCtrs.
4.3.19 Ct<layer>WaitThresholdHit register
The WaitThresholdHit registers are associated with a specific AHB layer:
•
CtArmdWaitThresholdHit
• CtArmiWaitThresholdHit
• CtDma0WaitThresholdHit
• CtDma1WaitThresholdHit
• CtClcdWaitThresholdHit
• CtExpWaitThresholdHit
• CtGxiRdAWaitThresholdHit
• CtGxiRdDWaitThresholdHit
• CtGxiWrAWaitThresholdHit.
These registers contain the number of stall instances that exceeded a maximum number
of wait states on the associated AHB layer specified by the associated threshold register.
The default threshold is 16. The count is disabled by default and can be controlled
through the AHBMONCtrlReg, and reset through the AHBMONRstCtrs.