Specifications

AHB Monitor
4-34 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
4.3.15 CtArmdPageWalk<x>
The ARM926 data AHB interface uses the SINGLE burst format with a specific
protection bits set to perform page table walks for either the instruction or data path:
•
CtArmdPageWalkD
• CtArmdPageWalkI.
These registers contain the total count of completed page table walk transactions that
have occurred on the ARM-D AHB layer for the Instruction or Data path. The count is
disabled by default and can be controlled through the AHBMONCtrlReg, and reset
through the AHBMONRstCtrs. The counters are also controlled by the DBGACK in
relation to configuration, see AHBMONCtrlReg on page 4-39.
4.3.16 Ct<layer>WaitTotal
The six wait registers are associated with a specific AHB layer:
•
CtArmdWaitTotal
• CtArmiWaitTotal
• CtDma0WaitTotal
• CtDma1WaitTotal
• CtClcdWaitTotal
• CtExpWaitTotal.
These registers contain the total count of wait states observed on the associated AHB
layer. The count is disabled by default and can be controlled through the
AHBMONCtrlReg, and reset through the AHBMONRstCtrs. The counters associated
with the ARM D and ARM I layers are also controlled by the DBGACK in relation to
configuration, see AHBMONCtrlReg on page 4-39.
4.3.17 Ct<layer>WaitNonSeqSlave
The NONSEQ slave wait count registers are associated with a specific AHB layer:
•
CtArmdWaitNonSeqSlave
• CtArmiWaitNonSeqSlave
• CtDma0WaitNonSeqSlave
• CtDma1WaitNonSeqSlave
• CtClcdWaitNonSeqSlave
• CtExpWaitNonSeqSlave.
These registers contain the total count of wait states incurred on the first transfer of a
burst caused by the slave on the associated AHB layer from the matrix or locally. The
count is disabled by default and can be controlled through the AHBMONCtrlReg, and