Specifications

AHB Monitor
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-33
4.3.12 Ct<layer>BurstIncr16
The INCR16 burst count registers are associated with a specific AHB layer that contains
a master that is capable of this burst format:
•
CtDma0BurstIncr16
• CtDma1BurstIncr16
• CtClcdBurstIncr16
• CtExpBurstIncr16.
These registers contain the total count, read + write, of completed INCR16 burst
transfers that have occurred on the associated AHB layer. The count is disabled by
default and can be controlled through the AHBMONCtrlReg, and reset through the
AHBMONRstCtrs.
4.3.13 CtArm<layer>LineFill
The ARM926 instruction and data AHB interfaces use the WRAP8 burst format to
perform cache line fills. There are two line file counters:
•
CtArmdLineFill
• CtArmiLineFill.
These registers contain the total count of completed cache line fill transactions, WRAP8
burst, that have occurred on the associated AHB ARM layer. The count is disabled by
default and can be controlled through the AHBMONCtrlReg, and reset through the
AHBMONRstCtrs. The counters are also controlled by the DBGACK in relation to
configuration, see AHBMONCtrlReg on page 4-39.
4.3.14 CtArmdCastOut<x>
The ARM926 data AHB interface uses the INCR4 burst format, with specific protection
bits set, to perform cache writebacks. The writeback can be either full or half cache line
writes:
•
CtArmdCastOut4
• CtArmdCastOut8.
These registers contain the total count of completed cache line writeback transactions
that have occurred on the ARM-D AHB layer. The count is disabled by default and can
be controlled through the AHBMONCtrlReg, and reset through the AHBMONRstCtrs.
The counters are also controlled by the DBGACK in relation to configuration, see
AHBMONCtrlReg on page 4-39.