Specifications
AHB Monitor
4-32 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
4.3.9 CtExpBurstWrap8
Only the EXPansion bus contains a master that is capable of issuing a WRAP8 burst
transfer that is referred to by the burst name, namely the AHB-AHB bridge, which
interfaces external AHB master components to the PWP environment. The
ARM926PXP also performs WRAP8 burst transfers, but the counts are referred by the
associated activity of a cache line fill.
This register contains the total count, read + write, of completed WRAP8 burst transfers
that have occurred on the EXPansion AHB layer. The count is disabled by default and
can be controlled through the AHBMONCtrlReg, and reset through the
AHBMONRstCtrs.
4.3.10 Ct<layer>BurstIncr8
The INCR8 burst count registers are associated with a specific AHB layer that contains
a master that is capable of this burst format. This description is valid for the following
registers:
•
CtArmdBurstIncr8
•
CtDma0BurstIncr8
•
CtDma1BurstIncr8
•
CtClcdBurstIncr8
•
CtExpBurstIncr8.
These registers contain the total count, read + write, of completed INCR8 burst transfers
that have occurred on the associated AHB layer. The count is disabled by default and
can be controlled through the AHBMONCtrlReg, and reset through the
AHBMONRstCtrs. The counter associated with the ARM D layer is also controlled by
the DBGACK in relation to configuration, see AHBMONCtrlReg on page 4-39.
4.3.11 CtExpBurstWrap16
Only the EXPansion bus contains a master that is capable of issuing a WRAP16 burst
transfer, the AHB-AHB bridge, which interfaces external AHB master components to
the PWP environment.
This register contains the total count, read + write, of completed WRAP16 burst
transfers that have occurred on the EXPansion AHB layer. The count is disabled by
default and can be controlled through the AHBMONCtrlReg, and reset through the
AHBMONRstCtrs.