Specifications

AHB Monitor
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-31
4.3.6 Ct<layer>BurstIncr
The read count registers are associated with a specific AHB layer that contains a master
that is capable of this burst format.
•
CtDma0BurstIncr
• CtDma1BurstIncr
• CtClcdBurstIncr
• CtExpBurstIncr.
These registers contain the total count, read + write, of completed unspecified length
burst transfers that have occurred on the associated AHB layer. The count is disabled by
default and can be controlled through the AHBMONCtrlReg, and reset through the
AHBMONRstCtrs.
4.3.7 CtExpBurstWrap4
Only the EXPansion bus contains a master that is capable of issuing a WRAP4 burst
transfer, the AHB-AHB bridge, which interfaces external AHB master components to
the PWP environment.
This register contains the total count, read + write, of completed WRAP4 burst transfers
that have occurred on the EXPansion AHB layer. The count is disabled by default and
can be controlled through the AHBMONCtrlReg, and reset through the
AHBMONRstCtrs.
4.3.8 Ct<layer>BurstIncr4
The INCR4 burst count registers are associated with a specific AHB layer that contains
a master that is capable of this burst format:
•
CtArmdBurstIncr4
• CtArmiBurstIncr4
• CtDma0BurstIncr4
• CtDma1BurstIncr4
• CtClcdBurstIncr4
• CtExpBurstIncr4.
These registers contain the total count, read + write, of completed INCR4 burst transfers
that have occurred on the associated AHB layer. The count is disabled by default and
can be controlled through the AHBMONCtrlReg, and reset through the
AHBMONRstCtrs. The counters associated with the ARM D and ARM I layers are also
controlled by the DBGACK in relation to configuration, see AHBMONCtrlReg on
page 4-39.