Specifications

AHB Monitor
4-30 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
These registers contain the total count of completed read transfers of all possible burst
types that have occurred on the DMA-0 AHB layer that have accessed a specific APB
slave. The count is disabled by default and can be controlled through the
AHBMONCtrlReg, and reset through the AHBMONRstCtrs. The counters associated
with the ARM D layer are also controlled by DBGACK in relation to configuration, see
AHBMONCtrlReg on page 4-39.
4.3.4 Ct<layer>Wr<x>
The specific write count register are associated with an access to a specific APB slave:
•
CtDma0WrUart
• CtDma0WrSci
• CtDma0WrSSP
• CtArmdWrApbDma
• CtArmdWrApbCore
• CtExpWrApbDma
• CtExpWrApbCore.
These registers contain the total count of completed write transfers of all possible burst
types that have occurred on the DMA-0 AHB layer that have accessed a specific APB
slave. The count is disabled by default and can be controlled through the
AHBMONCtrlReg, and reset through the AHBMONRstCtrs. The counters associated
with the ARM D layer are also controlled by the DBGACK in relation to configuration,
see AHBMONCtrlReg on page 4-39.
4.3.5 Ct<layer>BurstSingle
The SINGLE burst count registers are associated with a AHB layer that contains a
master that is capable of this burst format:
•
CtArmdBurstSingle
• CtArmiBurstSingle
• CtExpBurstSingle.
These registers contain the total count, read + write, of completed single burst transfers
that have occurred on the associated AHB layer. The count is disabled by default and
can be controlled through the AHBMONCtrlReg, and reset through the
AHBMONRstCtrs. The counters associated with the ARM D and ARM I layers are also
controlled by the DBGACK in relation to configuration, see AHBMONCtrlReg on
page 4-39.