Specifications

List of Figures
xiv Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
Figure 3-11 AHB memory map with bridge remap and SMC ..................................................... 3-23
Figure 3-12 AHB memory map with bridge remap and no SMC ................................................ 3-24
Figure 3-13 Supported address remap functionality for ARM D AHB ........................................ 3-25
Figure 3-14 Alias for REMAPSTATIC LOW ............................................................................... 3-26
Figure 3-15 Alias for REMAPSTATIC HIGH and MPMCnSMC LOW ........................................ 3-27
Figure 3-16 Alias for REMAPSTATIC HIGH and MPMCnSMC HIGH ....................................... 3-27
Figure 3-17 Alias for REMAPEXTERNAL HIGH and CFGBRIDGEMEMMAP HIGH ................ 3-28
Figure 3-18 Alias for REMAPEXTERNAL HIGH and CFGBRIDGEMEMMAP LOW ................. 3-28
Figure 3-19 APB map ................................................................................................................. 3-29
Figure 3-20 MBX map ................................................................................................................ 3-31
Figure 4-1 AHB monitor block diagram ...................................................................................... 4-3
Figure 4-2 AHB Monitor packet format ....................................................................................... 4-4
Figure 4-3 Peripheral ID register .............................................................................................. 4-40
Figure 4-4 PrimeCell ID register ............................................................................................... 4-41
Figure 5-1 CLCDC internal organization .................................................................................... 5-4
Figure 5-2 CLCDC block diagram .............................................................................................. 5-5
Figure 5-3 Hardware cursor block diagram ................................................................................ 5-7
Figure 5-4 Hardware cursor movement ..................................................................................... 5-9
Figure 5-5 Hardware cursor clipping ........................................................................................ 5-10
Figure 5-6 Hardware cursor image format ............................................................................... 5-11
Figure 5-7 ClcdCrsrCtrl Register bit assignments .................................................................... 5-18
Figure 5-8 ClcdCrsrConfig Register bit assignments ............................................................... 5-20
Figure 5-9 ClcdCrsrPalette0 and ClcdCrsrPalette1 Register bit assignments ......................... 5-21
Figure 5-10 ClcdCrsrXY Register bit assignments ..................................................................... 5-21
Figure 5-11 ClcdCrsrClip Register bit assignments ................................................................... 5-22
Figure 5-12 ClcdCrsrIMSC Register bit assignments ................................................................ 5-23
Figure 5-13 ClcdCrsrICR Register bit assignments ................................................................... 5-24
Figure 5-14 ClcdCrsrRIS Register bit assignments ................................................................... 5-25
Figure 5-15 ClcdCrsrMIS Register bit assignments ................................................................... 5-26
Figure 5-16 CLCDPeriphID0-3 Register bit assignments .......................................................... 5-27
Figure 5-17 CLCDCPCellID0-3 Register bit assignments .......................................................... 5-29
Figure 6-1 MOVE overview ........................................................................................................ 6-3
Figure 7-1 ARM MBX HR-S top level block diagram ................................................................. 7-2
Figure 7-2 MMU address translation .......................................................................................... 7-8
Figure 8-1 DMAC interface block diagram ................................................................................. 8-4
Figure 9-1 GPIO output control .................................................................................................. 9-3
Figure 10-1 MPMC PrimeCell block diagram ............................................................................. 10-6
Figure 11-1 PrimeCell RTC ........................................................................................................ 11-3
Figure 12-1 SCI block diagram .................................................................................................. 12-4
Figure 13-1 SSMC interface block diagram ............................................................................... 13-5
Figure 13-2 Address and control multiplexor ............................................................................. 13-6
Figure 13-3 Data multiplexor ...................................................................................................... 13-7
Figure 14-1 PrimeCell SSP block diagram ................................................................................. 14-3
Figure 15-1 Simplified block diagram ......................................................................................... 15-4
Figure 16-1 PrimeCell UART block diagram .............................................................................. 16-4
Figure 17-1 VIC block diagram ..................................................................................................
17-4
Figure 17-2 Interrupt request logic ............................................................................................. 17-5