Specifications

AHB Monitor
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-29
4.3.1 Ct<layer>Rd
There are six read count registers. Each is associated with a specific AHB layer:
•
CtArmdRd
• CtArmiRd
• CtDma0Rd
• CtDma1Rd
• CtClcdRd
• CtExpRd.
The registers contain the total count of completed read transfers of all possible burst types that
have occurred on the associated AHB layer. The count is disabled by default and can be controlled
through the AHBMONCtrlReg, and reset through the AHBMONRstCtrs. The counters associated
with the ARM D and ARM I layers are also controlled by the DBGACK in relation to
configuration, see
AHBMONCtrlReg on page 4-39.
4.3.2 Ct<layer>Wr
The write count registers are associated with a AHB layer that contains a master that is
write capable.
•
CtArmdWr
• CtDma0Wr
• CtDma0Rd
• CtExpWr.
The registers contain the total count of completed write transfers of all possible burst
types that have occurred on the associated AHB layer. The count is disabled by default
and can be controlled through the AHBMONCtrlReg, and reset through the
AHBMONRstCtrs. The counters associated with the ARM D layer are also controlled
by the DBGACK in relation to configuration, see AHBMONCtrlReg on page 4-39.
4.3.3 Ct<layer>Rd<x>
The specific read count registers are associated with an access to a specific APB slave
or APB bridge:
•
CtDma0RdUart
• CtDma0RdSci
• CtDma0RdSSP
• CtArmdRdApbDma.