Specifications

AHB Monitor
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-25
CtDma0WrSci 0x101D024C Counter. See Ct<layer>Wr<x> on page 4-30.
CtDma0RdSsp
0x101D0250 Counter. See Ct<layer>Rd<x> on page 4-29.
CtDma0WrSsp
0x101D0254 Counter. See Ct<layer>Wr<x> on page 4-30.
CtDma0BurstIncr
0x101D020C Counter. See Ct<layer>BurstIncr on page 4-31.
CtDma0BurstIncr4
0x101D0214 Counter. See Ct<layer>BurstIncr4 on page 4-31.
CtDma0BurstIncr8
0x101D021C Counter. See Ct<layer>BurstIncr8 on page 4-32.
CtDma0BurstIncr16
0x101D0224 Counter. See Ct<layer>BurstIncr16 on page 4-33.
CtDma0WaitTotal
0x101D0230 Counter. See Ct<layer>WaitTotal on page 4-34.
CtDma0WaitNonSeqSlave
0x101D0228 Counter. See Ct<layer>WaitNonSeqSlave on page 4-34.
CtDma0WaitNonSeqBus
0x101D022C Counter. See Ct<layer>WaitNonSeqBus on page 4-35.
CtDma0WaitThresholdHit
0x101D0234 Counter. See Ct<layer>WaitThresholdHit register on page 4-35.
Dma0WaitThreshold
0x101D0238 4-bit wide R/W Wait Threshold Register. See <layer>WaitThreshold
register on page 4-36.
CtDma1Rd
0x101D0300 Counter. See Ct<layer>Rd on page 4-29.
CtDma1Wr
0x101D0304 Counter. See Ct<layer>Wr on page 4-29.
CtDma1BurstIncr
0x101D030C Counter. See Ct<layer>BurstIncr on page 4-31.
CtDma1BurstIncr4
0x101D0314 Counter. See Ct<layer>BurstIncr4 on page 4-31.
CtDma1BurstIncr8
0x101D031C Counter. See Ct<layer>BurstIncr8 on page 4-32.
CtDma1BurstIncr16
0x101D0324 Counter. See Ct<layer>BurstIncr16 on page 4-33.
CtDma1WaitTotal
0x101D0330 Counter. See Ct<layer>WaitTotal on page 4-34.
CtDma1WaitNonSeqSlave
0x101D0328 Counter. See Ct<layer>WaitNonSeqSlave on page 4-34.
CtDma1WaitNonSeqBus
0x101D032C Counter. See Ct<layer>WaitNonSeqBus on page 4-35.
CtDma1WaitThresholdHit
0x101D0334 Counter. See Ct<layer>WaitThresholdHit register on page 4-35.
Dma1WaitThreshold
0x101D0338 4-bit wide R/W Wait Threshold Register. See <layer>WaitThreshold
register on page 4-36.
CtExpRd
0x101D0400 Counter. See Ct<layer>Rd on page 4-29.
Table 4-14 AHB Monitor registers (continued)
Name Address Description