Specifications

AHB Monitor
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-23
4.3 AHB Monitor registers
Many of the registers in the AHB monitor replicate behavior over two or more PWP
AHB layers. Therefore to minimize verboseness, the behaviors of the registers that
overlap are described together. The generic description is referred to by replacing the
reference to the specific AHB layer with <layer>:
Ct<layer>Rd
Ct<layer>Wr
Ct<layer>Rd<x>
Ct<layer>Wr<x>
Ct<layer>BurstSingle
Ct<layer>BurstIncr
CtExpBurstWrap4
Ct<layer>BurstIncr4
CtExpBurstWrap8
Ct<layer>BurstIncr8
CtExpBurstWrap16
Ct<layer>BurstIncr16
CtArm<x>LineFill
CtArmdCastOut<x>
CtArmdPageWalk<x>
Ct<layer>WaitTotal
Ct<layer>WaitNonSeqSlave
Ct<layer>WaitNonSeqBus
Ct<layer>WaitThresholdHit
<layer>WaitThreshold
CtGxiWr
CtGxiRd
CtGxiWrAddrWait
CtGxiRd<layer>Wait
CtGxiPageCount
CtGxiPageSize
AHBMONRstCtrs
AHBMONPrstCtrs
AHBMONCtrlReg
CtTotalCycles
CtTotalCyclesEn
CtTotalCyclesNonDebug
AHBMONPeriphID
AHBMONPCellID
The AHB Monitor registers are shown in Table 4-14 on page 4-24.
Unless specified otherwise, the registers are 32-bit wide counters, read only, and reset
to
0x0 on reset.