Specifications

AHB Monitor

Miscellaneous Counted Events with the AHB Monitor

Table 4-13 presents three additional counters included to enable the further evaluation

of the system based on the number of cycles elapsed dependent on certain operating

conditions. With exception of the CtTotalCycles, these counters are enabled through the

counter enable bit in the AHBMONCtrlReg register (see AHBMONCtrlReg on

page 4-39). The CtTotalCyclesNonDebug counter is controlled also by the DBGACK

and when the track DBGACK is asserted. The track DBGACK, when set, disables the

counter during cycles that the DBGACK is asserted. The latter two counters can be

reset by writing to the AHBMONRstCntrs register, and preset to their absolute address

by writing to the AHBMONPrstCntrs register.

Table 4-13 Other events

Counter Name Description

CtTotalCycles Number of bus cycles since the last hardware reset

CtTotalCyclesEn Number of bus cycles that the profile counters

have been enabled since the last hardware reset or

counter reset

CtTotalCyclesNonDebug Number of bus cycles that the profile counters

have been enabled since the last hardware reset or

counter reset discounting debug cycles, based on

DBGACK from the ARM processor