Specifications

AHB Monitor
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-21
Counted Events on the MBX GXI Layer
The MBX connects to the MPMC through a dedicated interconnect. The connection
performs single unit read and write transfers over logically disjoint data buses. Further
details of the interconnect are contained with the MBX TRM.
Table 4-12 shows all the events that are recorded on the MBX GXI bus. These counters
are enabled through the counter enable bit in the AHBMONCtrlReg. All counters can
be reset by writing to the AHBMONRstCntrs register, and preset to their absolute
address by writing to the AHBMONPrstCntrs register.
Table 4-12 GXI events
Counter Name Description
CtGxiWr Number of completed write transfers.
CtGxiRd Number of completed read requests.
CtGxiWrAddrWait Number of wait cycles suffered by write requests.
CtGxiRdAddrWait Number of wait cycles suffered by read requests.
CtGxiRdDataWait Number of wait cycles suffered by pending read transfers.
CtGxiRdAWaitThresholdHit Number of occurrences that a read request wait-state
exceeded a configurable threshold, not a count of how many
messages suffer the threshold latency.
CtGxiRdDWaitThresholdHit Number of occurrences that a read transfer wait-state
exceeded a configurable threshold.
CtGxiWrAWaitThresholdHit Number of occurrences that a write wait-state exceeded a
configurable threshold.
CtGxiPageChange Number of times the transfer crossed a page boundary. The
page boundary size can be configured to 2k, 4k, 8k or 16k.
GxiPageSize Defines the page size that the CtGxiPageChange counter
uses to monitor page boundary changes. 2'b00 = 2k, 2'b01 =
4k, 2'b10 = 8k, & 2'b11 = 16k.