Specifications

AHB Monitor

disables the counters during cycles that the DBGACK is asserted. All counters can be

reset by writing to the AHBMONRstCntrs register, and preset to their absolute address

by writing to the AHBMONPrstCntrs register.

Table 4-11 D layer events

Event Counter Name Description

CtArmdRd Total number of read transfers, including cache linefills and

page table walks,

CtArmdWr Total number of write transfers, including cache writebacks

CtArmdRdApbDma Total number of read transfers to the DMA peripherals

APB Bridge

CtArmdWrApbDma Total number of write transfers to the DMA peripherals

APB Bridge

CtArmdRdApbCore Total number of read transfers to the Core peripherals APB

Bridge

CtArmdWrApbCore Total number of write transfers to the Core peripherals

APB Bridge

CtArmdBurstSingle Number of single word bursts, including page table walks

CtArmdBurstIncr4 Number of 4-word incrementing bursts, including half line

cache writebacks

CtArmdBurstIncr8 Number of 8-word incrementing bursts, including full line

cache write backs

CtArmdLineFill Number of D-cache linefills, that is,

CtArmdRdBurstWrap8 - number of 8-word wrapping read

bursts.

CtArmdCastOut4 Number of half line cache writebacks,

that is, CtArmdWrBurstIncr4ProtCBPD - number of

4-word incrementing write bursts with particular HPROT.

This counter can also check for the INCR4 being 4-word

aligned in order to filter out approximately 75% of the STM

bursts that are incorrectly identified as cast-outs

CtArmdCastOut8 Number of full line cache writebacks, that is,

CtArmdWrBurstIncr8ProtCBPD - number of 8-word

incrementing write bursts with particular HPROT.