Specifications

AHB Monitor
4-18 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
Counted events on ARM-D layer
The ARM926EJ-S ARM-D BIU can perform all active AHB transfer types, that is reads
and writes of size 8-, 16- and 32-bits. It performs only burst types SING, INCR, INCR4,
INCR8, WRAP8 (Rd). Normal data transfers, cache operations and page table walks
can be differentiated by using a combination of transfer direction, burst type and
protection signal values.
There are no BUSY transfers on this layer.
Table 4-11 on page 4-19 shows all the events that are recorded on the ARM-D layer.
These counters are enabled through the counter enable bit in the AHBMONCtrlReg
register (see AHBMONCtrlReg on page 4-39) and are further controlled by the
DBGACK and when the track DBGACK is asserted. The track DBGACK, when set,
CtExpBurstWrap4 Number of 4-beat wrapping bursts
CtExpBurstIncr4 Number of 4-beat incrementing bursts
CtExpBurstWrap8 Number of 8-beat wrapping bursts
CtExpBurstIncr8 Number of 8-beat incrementing bursts
CtExpBurstWrap16 Number of 16-beat wrapping bursts
CtExpBurstIncr16 Number of 16-beat incrementing bursts
CtExpWaitTotal Total number of wait states
CtExpWaitNonSeqSlave Number of wait states on the first transfer of a burst
that were caused by a slave
CtExpWaitNonSeqBus Number of wait states on the first transfer of a burst
that were caused by the bus infrastructure
CtExpWaitThresholdHit Number of occurrences that a wait-state exceeded a
configurable threshold
Table 4-10 EXP layer events (continued)
Counter Name Description