Specifications

AHB Monitor

Counted events on DMA-1 layer

The PrimeCell PL080 DMAC BIU can perform all active AHB transfer types, that is,

reads and writes of size 8, 16, and 32-bits. It performs only burst types INCR, INCR4,

INCR8, and INCR16. DMA master number 1 is used to access memory either through

the memory controllers within the ARM926EJ-S Development Chip (SMC, MPMC) or

external slaves accessed through the off-chip bridges.

Table 4-9 shows all the events that are recorded on the DMA-1 layer. These counters are

enabled through the counter enable bit in the AHBMONCtrlReg register. All counters

can be reset by writing to the AHBMONRstCntrs register, and preset to their absolute

address by writing to the AHBMONPrstCntrs register.

CtDma0WaitNonSeqSlave Number of wait states on the first transfer of a burst that

were caused by a slave

CtDma0WaitNonSeqBus Number of wait states on the first transfer of a burst that

were caused by the bus infrastructure

CtDma0WaitThresholdHit Number of occurrences that a wait-state exceeded a

configurable threshold

Table 4-9 DMA 1 events

Counter Name Description

CtDma1Rd Total number of read transfers

CtDma1Wr Total number of write transfers

CtDma1BurstIncr Number of unspecified length bursts

CtDma1BurstIncr4 Number of 4-beat incrementing bursts

CtDma1BurstIncr8 Number of 8-beat incrementing bursts

CtDma1BurstIncr16 Number of 16-beat incrementing bursts

CtDma1WaitTotal Total number of wait states

Table 4-8 DMA 0 events (continued)

Counter Name Description