Specifications

AHB Monitor

Counted events on DMA-0 layer

The PrimeCell PL080 DMAC BIU can perform all active AHB transfer types, that is,

reads and writes of size 8, 16, and 32-bits. It performs only burst types INCR, INCR4,

INCR8, and INCR16. DMA master number 0 is used to access the three DMA-capable

peripherals within the ARM926EJ-S Development Chip (UART, SCI, SSP) or external

slaves accessed through the off-chip bridges.

The APB bridge generates the PSEL signal from a direct binary decode of

HADDR[15:12]. The resultant decode maps as:

PSEL[15:0] = {PSelExp[10:0], PSelSsp, PSelUart[2:0], PSelSCard}

Table 4-8 shows all the events that are recorded on the DMA-0 layer. These counters are

enabled through the counter enable bit in the AHBMONCtrlReg. All counters can be

reset by writing to the AHBMONRstCntrs register, and preset to their absolute address

by writing to the AHBMONPrstCntrs register.

Table 4-8 DMA 0 events

Counter Name Description

CtDma0Rd Total number of read transfers

CtDma0Wr Total number of write transfers

CtDma0RdUart Number of read transfers from the UART, there are

three selects for UART,

CtDma0WrUart Number of write transfers to the UART, there are three

selects for UART,

CtDma0RdSci Number of read transfers from the SCI

CtDma0WrSci Number of write transfers to the SCI

CtDma0RdSsp Number of read transfers from the SSP

CtDma0WrSsp Number of write transfers to the SSP

CtDma0BurstIncr Number of unspecified length bursts

CtDma0BurstIncr4 Number of 4-beat incrementing bursts

CtDma0BurstIncr8 Number of 8-beat incrementing bursts

CtDma0BurstIncr16 Number of 16-beat incrementing bursts

CtDma0WaitTotal Total number of wait states