Specifications

AHB Monitor

Counted events on ARM-I layer

The ARM926EJ-S ARM-I BIU performs only a small subset of AHB transfer types. It

performs no writes at all. All reads are word-sized, even when not in ARM state. For

example, two half-word Thumb instructions are fetched by one word transfer. It

performs only burst types SINGLE, INCR4, WRAP8 (I-cache line fills).

There are no BUSY transfers on this layer.

Table 4-6 shows all the events that are recorded on the ARM-I layer. These counters are

enabled through the counter enable bit in the AHBMONCtrlReg register and are further

controlled by the DBGACK and when the track DBGACK is asserted. The track

DBGACK, when set, disables the counters during cycles that the DBGACK is asserted.

All counters can be reset by writing to the AHBMONRstCntrs register, and preset to

their absolute address by writing to the AHBMONPrstCntrs register.

Table 4-6 Event counters for the ARM-I layer

Counter Name Description

CtArmiRd Total number of completed read transfers

CtArmiBurstSingle Number of single word bursts

CtArmiBurstIncr4 Number of 4-word incrementing bursts

CtArmiLineFill Number of I-cache linefills, that is, CtArmiBurstWrap8 -

number of 8-word wrapping bursts

CtArmiWaitTotal Total number of wait states

CtArmiWaitNonSeqSlave Number of wait states on the first transfer of a burst that were

caused by a slave

CtArmiWaitNonSeqBus Number of wait states on the first transfer of a burst that were

caused by the bus infrastructure

CtArmiWaitThresholdHit Number of occurrences that a wait-state exceeded a configurable

threshold