Specifications

AHB Monitor

As the AMBA AHB specification allows for divergent behavior in reaction to the

ERROR specification, the behavior of each of the AHB masters contained within the

ARM926EJ-S Development Chip design is shown below to help you understand the

profile information collected on each layer:

CLCDC It stops the current burst by issuing a bus idle and enters an error state that

issues an interrupt signal. Once the interrupt is cleared the controller

begins the frame again.

DMAC Halts the current burst then halts further bus activity and optionally raises

an interrupt.

AHB-AHB bridge

Passes errors back to the source master.

ARM926-I The burst transaction is always completed before an ABORT exception is

raised. Following the completion of the ABORT exception handler, the

ARM executes a specific instruction to execute the instruction that caused

the data abort.

ARM926-D If it occurs on a SWAP instruction, the write is always attempted. For all

other cases the BUI, always completes the burst transaction before raising

an ABORT exception. Following the completion of the ABORT

exception handler the ARM executes a specific instruction to execute the

instruction that caused the data abort.

Similarly to the AHB layers, statistical information is also collected for the GXI, such

as number of complete read and write transfers and stall trends.