Specifications

AHB Monitor

Accessing the Profiling Counters

The profiling counters of each layer are accessed through an AHB slave port. They are

only connected to the ARM-D and EXPansion bus layers at a base address of

0x101D0000

. The control and configuration registers for the profiling counter are also

accessible through this base address. Each register in the AHB monitor is word aligned.

Note

The enabling and clearing of the profiling counters is synchronized to the registered

operation of the associated layers to ensure that the data collected is correct.

Counted events

All the layers contain a number of counters for collecting statistical information, such

as number of basic accesses and burst behavior. Certain layers also contain additional

counters for layer specific or behavior of interest. For example:

• the ARM-I and ARM-D layers also contain counters for cache related statistics

• the ARM-D and EXP layers contain counters to track accesses to the APB bridges

• for the DMA peripheral layer (DMA0) the transfers to each of the built-in slaves

are counted independently as an easy means of determining which component

was using the most DMA bandwidth.

There are counters to help determine the mean latency experienced by each bus master

in the form of wait states. Latency caused by bus infrastructure or arbitration is typically

seen only on the first transfer of a burst. By differentiating between the two causes of

wait states for nonsequential transfers, and knowing the number of bursts, you get an

indication of the stalling effect of the bus infrastructure.

As each layer, with exception of the GXI, can receive an ERROR response and the

ARM-D layer can receive a RETRY response, it is important to define the count

behavior in regards to these condition:

• Read / Write counters increment on ERROR, second cycle, and OKAY responses

only

• burst counters increment on ERROR, second cycle, and OKAY responses only

• no increments occur with any other response.