Specifications

AHB Monitor

GXI Cycle States and Encoding

The GXI can perform concurrent read and write activities due to the split transfer

architecture it employs. Therefore, the four debug output pins related to the GXI are

divided into two, providing separate state information for the read and write channels.

The four bits dedicated to the GXI assign the upper two bits to the read channel and the

lower bits to the write channel, AHBMONITOR[32:29] = {ReadState, WriteState}.

Note

The GXI debug is a registered output based on the registered forms of the GXI bus

similar to the approach taken for the AHB layers, therefore the reported activity is

similarly delayed.

The two GXI channels behave differently and have different encoding presented in

Table 4-4 and Table 4-5 on page 4-10. Table 4-4 shows the states of the read data

channel and Table 4-5 on page 4-10 shows the states of the address channel.

Table 4-4 Bit patterns for GXI states for read channel

Symbol Name

Encoding

[32:31]

Description

I Idle 00 The GXI read data channel is idle, that is, no transfers are

active nor pending

WP Wait Pending 01 The GXI read data channel has been stalled and has one or

more transfers waiting for completion

TnP Transfer and

None Pending

10 The GXI read data channel is taking part in a transfer

without any further transfers wait for completion

TP Transfer and

Pending

11 The GXI read data channel is taking part in a transfer with

one or more additional transfers waiting for completion