Specifications

AHB Monitor
4-8 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
NR_APBCore, APB bridge to
Core peripherals
011101Y-- -Y-
NR_AHBMON, AHB Monitor
registers
011110Y-- -Y-
HRESET 0 1 1111 - - Y Y Y -
0x20- 0x2F, Unused 1 0 xxxx - - - - - -
NW_SMCCFG, SMC 1 1 0111 Y - - - - -
NW_MPMCCFG, MPMC config
registers
110000Y-- ---
NW_VIC, VIC registers 1 1 0010 Y - - - - -
NW_CLCDC, CLCDC registers 1 1 0011 Y - - - - -
NW_DMAC, DMAC registers 1 1 0100 Y - - - - -
NW_MBX, MBX registers 1 1 0101 Y - - - - -
0x36 - 0x37, Unused 1 1 011x - - - - - -
NR_SMCCFG, Read SMC
configuration
111000Y-- ---
NR_MPMCCFG, Read MPMC
configuration
111001Y-- ---
NR_VIC, Read from VIC 1 1 1010 Y - - - - -
NR_CLCDC, Read from CLCDC 1 1 1011 Y - - - - -
NR_DMAC, DMAC registers 1 1 1100 Y - - - - -
NR_MBX, MBX registers 1 1 1101 Y - - - - -
RN, Retry_Next 1 1 1110 Y - - - - -
HRESET, Bus reset 1 1 1111 - - - - - -
a. The ARM-D bus state code is 6-bits long.
b. The DMA-0, DMA-1, and EXP bus state codes are 5-bits long.
Table 4-3 Bus state bit patterns (continued)
Symbol and bus state
[5]
a
[4]
b
[3:0] ARM-D
[28:23]
ARM-I
[22:19]
DMA-0
[18:14]
DMA-1
[13:9]
EXP
[8:4]
LCD
[3:0]