Specifications

AHB Monitor
4-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
AHB Cycle State encoding
Table 4-3 shows the bit pattern encoding used for each of the possible Bus Cycle States
on each layer and shows which of those values can actually be generated by that layer
(boxes marked with a Y).
Note
The LCD and ARM-I layers can only generate bit patterns with bits [5] and [4] are held
at 0. Similarly, the EXPansion, DMA0, and DMA0 layers can only generate bit patterns
with bit [5] of the Code field at 0. There are six bits assigned to the ARM-D layer, five
to each of the DMA and Expansion layers, and four for the LCD, ARM-I and GXI
layers.
WS Third read transfer from slave 2 in a wrapping burst of 4, one wait state inserted by
the slave
S_WRAP4 -
WS Fourth read transfer from slave 2 in a wrapping burst of 4, one wait state inserted by
the slave
S_WRAP4 -
Table 4-2 Sample output (continued)
Pattern on bus Description
Table 4-3 Bus state bit patterns
Symbol and bus state
[5]
a
[4]
b
[3:0] ARM-D
[28:23]
ARM-I
[22:19]
DMA-0
[18:14]
DMA-1
[13:9]
EXP
[8:4]
LCD
[3:0]
I, Idle 000000Y YY YYY
S_INCR, Sequential_INCR 0 0 0001 - - Y Y Y Y
B, Busy 000010- -- -YY
S_INCR4, Sequential_INCR4 0 0 0011 Y Y Y Y Y Y
S_WRAP8, Sequential_WRAP8 0 0 0100 Y Y - - Y -
S_INCR8, Sequential_INCR8 0 0 0101 Y - Y Y Y Y
EN, Error Next 0 0 0110 Y Y Y Y Y Y