Specifications
AHB Monitor
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-5
The total number of different NRs and NWs states, that are valid, is dependent upon the
layer - some masters only perform reads and most have connections to only a subset of
the possible slaves. Similarly the number of valid Sb states is dependent upon the layer
because most masters are not capable of producing all possible burst types. For these
reasons, the format of the encoded signals has been developed to allow the bit allocation
per layer as stated in the previous section.
Assigning different states for Sequential and Nonsequential transfers means that it is
possible to reconstruct burst information from the data stream. It is not necessary to
identify either the transfer direction or the slave number in a sequential transfer because
the bus protocol defines that both of these must remain constant throughout a burst, so
is the same as the most recent NRs or NWs state. Similarly, it is not necessary to identify
the burst type in a nonsequential transfer because this is indicated in any subsequent
sequential transfers.
The Error_Next and Retry_Next responses are indicated during the first cycle of the two
cycle response sequence, which allows the progress of the burst in second cycle as can
occur with an error response.
Table 4-2 shows an example pattern of transfers and the data stream produced.
Table 4-2 Sample output
Pattern on bus Description
I Idle Transfer
WB First write transfer to slave 1 incurring one wait state imposed by the bus matrix
NW1 -
S_INCR4 Second write transfer to slave 1 in an incrementing burst of four
S_INCR4 Third write transfer to slave 1 in an incrementing burst of four
S_INCR4 Fourth write transfer to slave 1 in an incrementing burst of four
WB First read transfer from slave 2, one wait states from the bus connect latency and one
from the arbitration latency
WA -
NR2 -
WS Second read transfer from slave 2 in a wrapping burst of 4, one wait state inserted by
the slave
S_WRAP4 -