Specifications

AHB Monitor

AHB Monitor packet format

There are 33 bits per data packet. To simplify the subsequent analysis of the data, there

are completely separate groups of bits associated with each AHB layer and the GXI.

The packet can be viewed as seven independent subpackets as shown in Figure 4-2.

There are six bits assigned to the ARM-D layer, five to each of the DMA and Expansion

layers, and four for the LCD, ARM-I and GXI layers.

Figure 4-2 AHB Monitor packet format

AHB Layer Cycle States

The states that can be reported for an AHB layer are shown in Table 4-1.

GXI

13 0414

89181922232829 332

ARM-D ARM-I DMA-0 DMA-1 EXP LCD

Table 4-1 Cycle states

Symbol Name Description

I Idle The bus master is performing, and hence completing, an IDLE transfer.

B Busy The bus master is performing, and hence completing, a BUSY transfer.

EN Error_Next The bus master is receiving the first half of an ERROR response.

RN Retry_Next The bus master is receiving the first half of a RETRY response.

WS Wait_Slave The bus master is incurring a wait state as a result of the slave.

WB Wait_Bus The bus master is incurring a wait state as a result of the matrix latency on

a new connection.

WA Wait_Arbiter The bus master is incurring a wait state as a result of the arbitration latency

of competing masters.

Sb Sequential_Burst_Type_b The bus master is completing a data transfer sequential to the last one. Set

of states representing each possible burst type.

NRs NewReadSlave_s The bus master is completing a Nonsequential Read from slave number

<s>

NWs NewWriteSlave_s The bus master is completing a Nonsequential Write to slave number <s>