Specifications

AHB Monitor

4.2 Functional description

The AHB monitor interface is shown in Figure 4-1.

Figure 4-1 AHB monitor block diagram

The base address of the AHB monitor is at

0x101D0000–0x101DFFFF

4.2.1 Bus Cycle Analyzer

The Bus Cycle Analyzer (BCA) provides information about bus activity on a cycle by

cycle basis. A packet of information is created on every bus clock. Access to the

real-time status of the layers is made available through a set of pins on the chip named

AHBMONITOR. Use the AHBMONITOR connections to monitor the activity of the

AHB interconnects through a logic analyzer.

The AHBMONITOR port

The AHBMONITOR port consists of 33 data output pins that export status data

packets at the AHB clock rate. A localized clock is exported on AHBMONITOR[33].

To produce minimal loading effects on the respective bus layers and to improve setup

and hold characteristics, the logic in the BCA includes registers to de-pipeline that part

of the information that it captured from the address phase. The registering of these

signals causes the status reported at the port to be three HCLK cycles behind the actual

activity on the interconnect.

ARM926EJ-S Dev. Chip

AHB monitor

AHBMONITOR[33:0]

ARM D layer signals

Bus

matrix

AHB control and

configuration

interface

ARM I layer signals

DMA 0 layer signals

DMA 1 layer signals

CLCDC layer signals

Expansion layer signals

MBX GXI signals

Layer

monitors