Specifications

Memory Map and Memory Configuration

HRESPM2[1:0] Input The transfer response provides additional information on the status of a

transfer. Two different responses are provided, OKAY and ERROR.

HDATAM2[31:0] Bidirectional Read/write data bus.

HCLKM2 Input Asynchronous AHB bus clock from an external source.

Table 3-3 AHB S signals

Signal Name Type Description

HMASTLOCKS Input Master lock signal. When HIGH, this signal indicates that the master on the

bus requires locked access and no other master should be granted the bus until

this signal is LOW.

HSELS Input Slave select.

HADDRS[31:0] Input System address bus, least significant 20 bits, driven by the active bus master.

HWRITES Input Transfer direction signal. When HIGH, this signal indicates a write to a slave

and when LOW a read from a slave.

HTRANSS[1:0] Input Indicates the type of the current transfer, which can be NONSEQUENTIAL,

SEQUENTIAL, IDLE or BUSY.

HSIZES[1:0] Input Transfer size signal. This signal indicates the size of the current transfer,

which can be byte (8-bit), halfword (16-bit), or word (32-bit).

HBURSTS[2:0] Input Indicates if the transfer forms part of a burst. Four, eight and 16 beat bursts

are supported and the burst can be either incrementing or wrapping.

HPROTS[3:0] Input The protection control signals provide additional information about a bus

access. They are primarily intended for use by any module that wished to

implement some level of protection.

HREADYS Bidirectional Transfer done. When HIGH indicates that a transfer has finished on the bus.

This signal can be driven LOW to extend a transfer.

HRESPS[1:0] Tristate output The transfer response provides additional information on the status of a

transfer. Two different responses are provided, OKAY and ERROR.

HDATAS[31:0] Bidirectional Read/write data bus.

HCLKS Input Asynchronous AHB bus clock from an external source.

Table 3-2 AHB M2 signals (continued)

Signal Name Type Description