Specifications
Memory Map and Memory Configuration
3-32 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
3.3 AHB signals to pads
This section describes the AHB signals on the input/output pads.
Note
The HDATAM2[28:0] signals on the AHB M2 bus are also used for the configuration
signals CFGDATA[28:0], see External configuration signals on page 2-19.
Table 3-1 AHB M1 signals
Signal Name Type Description
HBUSREQM1 Output Bus request. A signal from the master to the arbiter, which indicates that the
master interface requires the bus.
HLOCKM1 Output When HIGH this signal indicates that the master requires locked access to the
bus and no other master should be granted the bus until this signal is LOW.
HGRANTM1 Input Bus grant. This signal indicates that the master interface is currently the
highest priority master. Ownership of the address / control signals changes at
the end of a transfer when HREADYM is HIGH, so the master gets access to
the bus when both HREADYM and HGRANTM are HIGH.
HADDRM1[31:0] Tristate output System address bus, least significant 20 bits, driven by the active bus master.
HWRITEM1 Tristate output Transfer direction signal. When HIGH, this signal indicates a write to a slave
and when LOW a read from a slave.
HTRANSM1[1:0] Tristate output Indicates the type of the current transfer, which can be NONSEQUENTIAL,
SEQUENTIAL, IDLE or BUSY.
HSIZEM1[1:0] Tristate output Transfer size signal. This signal indicates the size of the current transfer,
which can be byte (8-bit), halfword (16-bit), or word (32-bit).
HBURSTM1[2:0] Tristate output Indicates if the transfer forms part of a burst. Four, eight and 16 beat bursts
are supported and the burst can be either incrementing or wrapping.
HPROTM1[3:0] Tristate output The protection control signals provide additional information about a bus
access. They are primarily intended for use by any module that wished to
implement some level of protection.
HREADYM1 Input Transfer completed input. When HIGH the signal indicates that a transfer has
finished on the bus. This signal can be driven LOW to extend a transfer.