Specifications

Memory Map and Memory Configuration
3-30 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
The DMA APB address map is listed in Table 3-1. The DMA APB is not accessible by
the ARM I, CLCD, or DMA1 masters. Accesses from these masters are routed to an
off-chip bridge.
The Core APB address map is listed in Table 3-2. The Core APB is not accessible by
the ARM I, CLCD, DMA0, or DMA1 masters. Accesses from these masters are routed
to an off-chip bridge.
Table 3-1 DMA APB peripheral base addresses
Base
address
Base name Peripheral
0x101F4000 SSP Synchronous Serial Port
0x101F3000 UART2 UART two
0x101F2000 UART1 UART one
0x101F1000 UART0 UART zero
0x101F0000 SCI Smart Card Interface
Table 3-2 Core APB peripheral base addresses
Base
address
Base name Peripheral
0x101E8000 RTC RTC
0x101E7000 GPIO3 GPIO port three
0x101E6000 GPIO2 GPIO port two
0x101E5000 GPIO1 GPIO port one
0x101E4000 GPIO0 GPIO port zero
0x101E3000 Timer2_3 Timer modules 2 and 3
0x101E2000 Timer0_1 Timer modules 0 and 1
0x101E1000 Watchdog Watchdog module
0x101E0000 SCTL System Controller