Specifications

Memory Map and Memory Configuration
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 3-29
3.2.6 APB address maps
Figure 3-19 shows the Core APB and DMA APB memory organization.
Figure 3-19 APB map
0x101FFFFF
0x101F400
0x101E0000
ARM DExpansion AHB S DMA0
0x101F0000
0x101F1000
0x101F2000
0x101F3000
0x101E1000
0x101E2000
0x101E3000
0x101E4000
0x101E5000
0x101E6000
0x101E7000
0x101E8000
0x101E9000
Sys. Controller
Watchdog
Timer 0&1
Timer 2&3
GPIO 0
GPIO 1
GPIO 2
GPIO 3
RTC
SCI
UART 0
UART 1
UART 2
SSP
0x101EFFFF
AHB Bridge to Off-
chip Peripherals
Sys. Controller
Watchdog
Timer 0&1
Timer 2&3
GPIO 0
GPIO 1
GPIO 2
GPIO 3
RTC
SCI
UART 0
UART 1
UART 2
SSP
AHB Bridge 2 to Off-
chip Peripherals
AHB Bridge 2 to Off-
chip Peripherals
SCI
UART 0
UART 1
UART 2
SSP
AHB Bridge 2 to Off-
chip Peripherals
AHB Bridge 2 to Off-
chip Peripherals
ARM I, CLCD & DMA1
AHB Bridge to Off-
chip Peripherals
AHB Bridge 2 to Off-
chip Peripherals
0x101F500