Specifications

Memory Map and Memory Configuration
3-28 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
Figure 3-17 shows the internal bus map for:
• REMAPSTATIC HIGH
• MPMCnSMC HIGH (the MPMC controls static memory)
• CFGBRIDGEMEMMAP HIGH (AHB M1 access selected by address range)
• REMAPEXTERNAL HIGH (boot memory is controlled off-chip).
Figure 3-17 Alias for REMAPEXTERNAL HIGH and CFGBRIDGEMEMMAP HIGH
Figure 3-18 shows the internal bus map for:
• REMAPSTATIC HIGH
• MPMCnSMC HIGH (the MPMC controls static memory)
• CFGBRIDGEMEMMAP LOW (AHB M1 access selected by master used)
• REMAPEXTERNAL HIGH (boot memory is controlled off-chip).
Figure 3-18 Alias for REMAPEXTERNAL HIGH and CFGBRIDGEMEMMAP LOW
0x00000000
0x10000000
AHB Bridge 2
to
Off-chip
Peripherals
AHB Bridge 2
to
Off-chip
Peripherals
0x0FFFFFFF
AHB Bridge 2
to
Off-chip
Peripherals
MPMCDYCS1
MPMCDYCS0
AHB Bridge 2
to
Off-chip
Peripherals
AHB Bridge 2 AHB Bridge 2AHB Bridge 2
Expansion
AHB S
DMA0 AHB
ARM I, CLCD &
DMA1 AHB
ARM D AHB
MPMCDYCS0 MPMCDYCS0
MPMCDYCS1 MPMCDYCS1
0x00000000
0x10000000
AHB Bridge 2
to
Off-chip
Peripherals
AHB Bridge 2
to
Off-chip
Peripherals
0x0FFFFFFF
AHB Bridge 2
to
Off-chip
Peripherals
MPMCDYCS1
MPMCDYCS0
AHB Bridge 1
to
Off-chip
Peripherals
AHB Bridge 2 AHB Bridge 1AHB Bridge 2
ARM D AHB
ARM I, CLCD &
DMA1 AHB
DMA0 AHB
Expansion
AHB S
MPMCDYCS1
MPMCDYCS0
MPMCDYCS1
MPMCDYCS0