Specifications

List of Tables
x Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
Table 4-5 Bit patterns for GXI state for address channel ........................................................ 4-10
Table 4-6 Event counters for the ARM-I layer ......................................................................... 4-13
Table 4-7 CLCDC events ........................................................................................................ 4-14
Table 4-8 DMA 0 events ......................................................................................................... 4-15
Table 4-9 DMA 1 events ......................................................................................................... 4-16
Table 4-10 EXP layer events .................................................................................................... 4-17
Table 4-11 D layer events ......................................................................................................... 4-19
Table 4-12 GXI events .............................................................................................................. 4-21
Table 4-13 Other events ........................................................................................................... 4-22
Table 4-14 AHB Monitor registers ............................................................................................. 4-24
Table 4-1 <layer>WaitThreshold ............................................................................................. 4-36
Table 4-1 GxiPageSize ........................................................................................................... 4-38
Table 4-2 AHBMONCtrlReg .................................................................................................... 4-39
Table 4-1 AHBMONPeriphID .................................................................................................. 4-40
Table 4-1 Output pad signal descriptions ............................................................................... 4-42
Table 5-1 PrimeCell CLCDC register differences ..................................................................... 5-6
Table 5-2 Supported cursor images .......................................................................................... 5-8
Table 5-3 32x32 cursor base addresses ................................................................................. 5-12
Table 5-4 LBBP buffer to pixel mapping 32x32 Cursor0 for datawords [31:16] ...................... 5-12
Table 5-5 LBBP buffer to pixel mapping 32x32 Cursor0 for datawords [15:0] ........................ 5-13
Table 5-6 LBBP buffer to pixel mapping 64x64 for datawords [31:16] .................................... 5-13
Table 5-7 LBBP buffer to pixel mapping 64x64 for datawords [15:0] ...................................... 5-14
Table 5-8 32x32 software mask storage ................................................................................. 5-15
Table 5-9 64x64 software mask storage ................................................................................. 5-15
Table 5-10 Pixel encoding ........................................................................................................ 5-16
Table 5-1 PrimeCell CLCDC register summary ...................................................................... 5-17
Table 5-2 ClcdCrsrCtrl Register bit assignments .................................................................... 5-19
Table 5-3 ClcdCrsrConfig Register bit assignments ............................................................... 5-20
Table 5-4 ClcdCrsrPalette0 and ClcdCrsrPalette1 Register bit assignments ......................... 5-21
Table 5-5 ClcdCrsrXY Register bit assignments ..................................................................... 5-22
Table 5-6 ClcdCrsrClip Register bit assignments ................................................................... 5-23
Table 5-7 ClcdCrsrIMSC Register bit assignments ................................................................ 5-24
Table 5-8 ClcdCrsrICR Register bit assignments ................................................................... 5-24
Table 5-9 ClcdCrsrRIS Register bit assignments ................................................................... 5-25
Table 5-10 ClcdCrsrMIS Register bit assignments ................................................................... 5-26
Table 5-11 Peripheral Identification Register options ............................................................... 5-27
Table 5-12 CLCDPeriphID0 Register bit assignments .............................................................. 5-28
Table 5-13 CLCDPeriphID1 Register bit assignments .............................................................. 5-28
Table 5-14 CLCDPeriphID2 Register bit assignments .............................................................. 5-28
Table 5-15 CLCDPeriphID3 Register bit assignments .............................................................. 5-28
Table 5-16 CLCDPCellID0 Register bit assignments ............................................................... 5-29
Table 5-17 CLCDPCellID1 Register bit assignments ............................................................... 5-29
Table 5-18 CLCDPCellID2 Register bit assignments ............................................................... 5-30
Table 5-19 CLCDPCellID3 Register bit assignments ............................................................... 5-30
Table 5-20 External pad output signals .................................................................................... 5-31
Table 7-1 MBX HR-S memory map .......................................................................................... 7-6
Table 8-1 DMA channel allocation ............................................................................................ 8-5