ARM926EJ-S Development Chip Reference Manual Copyright © 2004, 2006 ARM Limited. All rights reserved.
ARM926EJ-S Development Chip Reference Manual Copyright © 2004, 2006 ARM Limited. All rights reserved. Release Information Change history Description Issue Change April 2004 A New document August 2006 B Second release, updated to fix defects on AHB monitor and AHB bus graphics. Proprietary Notice Words and logos marked with® or ™ are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice.
Conformance Notices This section contains conformance notices. Federal Communications Commission Notice This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c). CE Declaration of Conformity A system using this development chip should be powered down when not in use. The ARM926PXP development chip generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications.
iv Copyright © 2004, 2006 ARM Limited. All rights reserved.
Contents ARM926EJ-S Development Chip Reference Manual Preface About this document .................................................................................. xviii Feedback ................................................................................................... xxiii Part A Chapter 1 Introduction and Configuration Introduction 1.1 1.2 1.3 Chapter 2 System Controller and Configuration Logic 2.1 2.2 2.3 2.4 2.5 2.6 ARM DDI 0287B About the ARM926EJ-S Development Chip ..................
Contents Chapter 3 Memory Map and Memory Configuration 3.1 3.2 3.3 Part B Chapter 4 Controllers and Peripherals AHB Monitor 4.1 4.2 4.3 4.4 Chapter 5 About the ARM PrimeCell MPMC (GX175) .............................................. 10-2 Functional description ............................................................................... 10-6 MPMC signals on pads ............................................................................. 10-8 Real-Time Clock (RTC) 11.1 11.
Contents Chapter 12 Smart Card Interface (SCI) 12.1 12.2 12.3 Chapter 13 Synchronous Static Memory Controller (SSMC) 13.1 13.2 13.3 Chapter 14 About the Watchdog module (SP805) ...................................................... 19-2 Functional description ............................................................................... 19-3 Pad signals by function ............................................................................... A-2 Mechanical and Electrical Specifications B.1 B.
Contents Appendix C Timing Specification C.1 C.2 C.3 C.4 viii About the timing parameters ...................................................................... AHB bus timing ........................................................................................... Memory timing ............................................................................................ Peripheral timing .........................................................................................
List of Tables ARM926EJ-S Development Chip Reference Manual Table 1-1 Table 2-1 Table 2-1 Table 2-2 Table 2-3 Table 2-4 Table 2-5 Table 2-6 Table 2-7 Table 2-8 Table 3-1 Table 3-1 Table 3-2 Table 3-1 Table 3-2 Table 3-3 Table 4-1 Table 4-2 Table 4-3 Table 4-4 ARM DDI 0287B Change history .............................................................................................................. ii MPMC port allocation .....................................................................................
List of Tables Table 4-5 Table 4-6 Table 4-7 Table 4-8 Table 4-9 Table 4-10 Table 4-11 Table 4-12 Table 4-13 Table 4-14 Table 4-1 Table 4-1 Table 4-2 Table 4-1 Table 4-1 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 5-6 Table 5-7 Table 5-8 Table 5-9 Table 5-10 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 5-6 Table 5-7 Table 5-8 Table 5-9 Table 5-10 Table 5-11 Table 5-12 Table 5-13 Table 5-14 Table 5-15 Table 5-16 Table 5-17 Table 5-18 Table 5-19 Table 5-20 Table 7-1 Table 8-1 x Bit p
List of Tables Table 8-1 Table 9-1 Table 9-2 Table 10-1 Table 12-1 Table 12-2 Table 13-1 Table 13-2 Table 14-1 Table 16-1 Table 17-1 Table 17-2 Table 18-1 Table A-1 Table B-1 Table B-2 Table B-3 Table C-1 Table C-2 Table C-3 ARM DDI 0287B DMA request and response signal descriptions ........................................................ 8-7 On-chip signal descriptions ....................................................................................... 9-4 Pad signal descriptions ....................
List of Tables xii Copyright © 2004, 2006 ARM Limited. All rights reserved.
List of Figures ARM926EJ-S Development Chip Reference Manual Figure 1-1 Figure 1-2 Figure 1-3 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 2-7 Figure 2-8 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 3-7 Figure 3-8 Figure 3-9 Figure 3-10 ARM DDI 0287B Typical application ..................................................................................................... 1-2 ARM926EJ-S Development Chip block diagram ..................................
List of Figures Figure 3-11 Figure 3-12 Figure 3-13 Figure 3-14 Figure 3-15 Figure 3-16 Figure 3-17 Figure 3-18 Figure 3-19 Figure 3-20 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 Figure 5-6 Figure 5-7 Figure 5-8 Figure 5-9 Figure 5-10 Figure 5-11 Figure 5-12 Figure 5-13 Figure 5-14 Figure 5-15 Figure 5-16 Figure 5-17 Figure 6-1 Figure 7-1 Figure 7-2 Figure 8-1 Figure 9-1 Figure 10-1 Figure 11-1 Figure 12-1 Figure 13-1 Figure 13-2 Figure 13-3 Figure 14
List of Figures Figure 17-3 Figure 17-4 Figure 17-5 Figure 17-6 Figure 19-1 Figure B-1 Figure C-1 ARM DDI 0287B Nonvectored FIQ interrupt logic .............................................................................. 17-6 Nonvectored IRQ interrupt logic .............................................................................. 17-6 Vectored interrupt block .......................................................................................... 17-7 Interrupt priority logic ...................
List of Figures xvi Copyright © 2004, 2006 ARM Limited. All rights reserved.
Preface This preface introduces the ARM926EJ-S Development Chip Reference Manual. It contains the following sections: • About this document on page xviii • Feedback on page xxiii. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
Preface About this document This document provides an overview of the ARM926EJ-S Development Chip and a description of the modules in it. For details on the registers and programmer’s interface, see the Technical Reference Manual for the individual controller. Intended audience This document has been written for experienced hardware and software developers using the ARM926EJ-S Development Chip as part of an existing development system.
Preface Chapter 9 General Purpose Input Output (GPIO) Read this chapter for a description of the GPIO. Chapter 10 Multi-Port Memory Controller (MPMC) Read this chapter for a description of the MPMC. Chapter 11 Real-Time Clock (RTC) Read this chapter for a description of the RTC controller. Chapter 12 Smart Card Interface (SCI) Read this chapter for a description of the SCI. Chapter 13 Synchronous Static Memory Controller (SSMC) Read this chapter for a description of the SSMC.
Preface Typographical conventions The following typographical conventions are used in this document: bold Highlights ARM signal names within text, and interface elements such as menu names. This style is also used for emphasis in descriptive lists where appropriate. italic Highlights special terminology, cross-references and citations. monospace Denotes text that can be entered at the keyboard, such as commands, file names and program names, and source code.
Preface The following publications provide reference information about the ARM architecture: • AMBA™ Specification (ARM IHI 0011) • ARM Architecture Reference Manual (ARM DDI 0100).
Preface • • ARM PrimeCell Watchdog Controller (SP805) Technical Reference Manual (ARM DDI 0270) ETM9 Technical Reference Manual (ARM DDI 0157) Other publications The following publication describes the JTAG ports with which Multi-ICE communicates: • xxii IEEE Standard Test Access Port and Boundary Scan Architecture (IEEE Std. 1149.1). Copyright © 2004, 2006 ARM Limited. All rights reserved.
Preface Feedback ARM Limited welcomes feedback both on the ARM926EJ-S Development Chip and on the documentation. Feedback on this document If you have any comments about this document, send email to errata@arm.com giving: • the document title • the document number • the page number(s) to which your comments refer • an explanation of your comments. General suggestions for additions and improvements are also welcome.
Preface xxiv Copyright © 2004, 2006 ARM Limited. All rights reserved.
Part A Introduction and Configuration
Chapter 1 Introduction This chapter introduces the ARM926EJ-S Development Chip. It contains the following sections: • About the ARM926EJ-S Development Chip on page 1-2 • Functional description on page 1-4 • External interfaces on page 1-9. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
Introduction 1.1 About the ARM926EJ-S Development Chip The ARM926EJ-S Development Chip is used in ARM development boards and enables you to develop software for products based on the ARM926EJ-S PrimeXSys Wireless Platform. A typical application of the ARM926EJ-S Development Chip is shown in Figure 1-1.
Introduction The block diagram in Figure 1-2 shows the internal buses and the master and slave bus interfaces. ETM9 ARM926EJ-S ARM Data AHB ARM Instruction AHB CLCDC AHB DMA1 AHB EXP AHB DMA0 AHB M CLCDC (PL110) config S M M config S DMAC (PL080) VIC (PL190) config S M S M Bus interface S S S S S S config S S AHB Mon.
Introduction 1.2 Functional description The ARM926EJ-S Development Chip comprises the following functional blocks: ARM926EJ-S This is a cached ARM CPU including Instruction and Data caches, Memory Management Unit (MMU), and Tightly Coupled Memory (TCM). It supports the JazelleTM extensions for Java acceleration. The ARM926EJ-S processor used with the ARM926EJ-S Development Chip is configured with 32KB instruction and data caches and 32KB TCMs. The release version used is ARM926EJ-S r0p3-00rel0.
Introduction AHB Monitor The AHB Monitor block outputs transaction information for the buses in the ARM926EJ-S Development Chip and is used to evaluate performance and bandwidth utilization analysis. For more information on the AHB monitor, see Chapter 4 AHB Monitor. MBX Graphics Accelerator The ARM MBX HR-S is a graphics accelerator that operates on 3D scene data. Triangles are written directly to the Tile Accelerator on a First In First Out (FIFO) basis so that the CPU is not stalled.
Introduction Direct Memory Access Controller (DMAC) Direct memory access can be used with DMA peripherals. FIFO fill and empty requests from these peripherals can be serviced immediately by the DMAC without CPU interaction. Memory-to-memory DMA is also supported. The release version used is PL080 DMAC REL1v1. For more information on DMA, see the ARM PrimeCell DMA (PL080) Technical Reference Manual and Chapter 8 Direct Memory Access Controller (DMAC).
Introduction For more information on the timers, see the ARM Dual-Timer Module (SP804) Technical Reference Manual and Chapter 15 Dual Timer/Counters. Watchdog module This is used to trigger a system reset in the event of software failure. The release version used is SP805 WDOG r1p0-02ltd0. For more information on the Watchdog monitor, see the ARM PrimeCell Watchdog Controller (SP805) Technical Reference Manual and Chapter 19 Watchdog Timer.
Introduction For more information on the CLCDC, see the ARM PrimeCell Color LCD Controller (PL110) Technical Reference Manual and Chapter 5 Color LCD Controller (CLCDC). General Purpose Input/Output (GPIO) interface There are four GPIO interfaces in the ARM926EJ-S Development Chip. Each GPIO interface provides eight programmable inputs or outputs. The release version used is PL061 GPIO 1v0.
Introduction 1.3 External interfaces The ARM926EJ-S Development Chip supports the following external interfaces: ARM DDI 0287B • three AHB expansion ports: — two master ports — one slave port.
Introduction 1.3.1 External memory support Two memory interfaces are provided to support external static memory and external SDRAM. When modeling high-performance systems, both memory interfaces can be used in parallel. In this configuration, the Synchronous Static Memory Controller PrimeCell PL093 drives the static memory interface and the Multiport Memory Controller PrimeCell GX175 drives the SDRAM memory interface. When modeling a relatively low-performance system, one memory interface can be used.
Introduction Default memory map The default memory map is divided into the regions shown in Figure 1-3 on page 1-12.
Introduction ARM D bus AHB Bridge to Off-chip Peripherals MPMC SDRAM MPMCDYCS3 MPMCDYCS2 AHB Bridge to Off-chip Peripherals MBX nSTATICCS3 nSTATICCS2 nSTATICCS1 nSTATICCS0 nSTATICCS7 nSTATICCS6 nSTATICCS5 nSTATICCS4 SSMC static memory SSMC static memory AHB Bridge to Off-chip Peripherals DMA APB Core APB AHB Monitor AHB Bridge to Off-chip Peripherals VIC DMAC CLCD MPMC configuration registers SMC configuration registers AHB Bridge to Off-chip Peripherals MPMC SDRAM MPMCDYCS1 MPMCDYCS0 0xFFFFFFFF 0x80
Introduction 1.3.2 DMA support The PrimeCell Dual-Master DMAC is provided to take full advantage of the multilayer AHB architecture. This enables memory-to-memory data transfers to be performed anywhere in the ARM926EJ-S Development Chip address space. Additionally, DMA handshake signals are provided, enabling memory-to-peripheral and peripheral-to-memory transfers to be supported. Sixteen peripheral DMA request interfaces are provided by the PrimeCell DMAC.
Introduction 1-14 Copyright © 2004, 2006 ARM Limited. All rights reserved.
Chapter 2 System Controller and Configuration Logic This chapter describes the system controller and configuration logic in the ARM926EJ-S Development Chip. It contains the following sections: • About the System Controller on page 2-2 • Clock control on page 2-13 • External configuration signals on page 2-19 • JTAG logic on page 2-25 • Implementation details for the ARM926EJ-S and system controller on page 2-28 • Control, configuration, and test signals on pads on page 2-30.
System Controller and Configuration Logic 2.1 About the System Controller The System Controller in the ARM926EJ-S Development Chip is used to provide an interface to control the operation of the chip.
System Controller and Configuration Logic 2.1.2 Interrupt response mode To enable the best possible response to interrupts, you can override the present mode bits in the System Control register after an interrupt has been generated. This enables, for example, the state machine to move from the DOZE mode to NORMAL mode after an interrupt.
System Controller and Configuration Logic 2.1.4 Low battery handling Two inputs are provided to the ARM926EJ-S Development Chip to facilitate software implementation of low battery and emergency power failure situations. These are: BATOK This input is an alternate function of GPIO3[7] and tells the software that there is sufficient charge in the battery for normal operation. When this input is inactive the system must not move into an operating mode that requires higher power consumption.
System Controller and Configuration Logic Figure 2-1 Enable signal generation for the Timer and Watchdog modules The module enable signals are: • WDOGCLKEN for the Watchdog module • TIMERCLKEN0 for timer clock enable 0 • TIMERCLKEN1 for timer clock enable 1 • TIMERCLKEN2 for timer clock enable 2 • TIMERCLKEN3 for timer clock enable 3. The enable signal for the Watchdog module is generated from the REFCLK input.
System Controller and Configuration Logic The Watchdog module enable is generated from the REFCLK input and a single WDOGCLKEN pulse is generated on every rising edge of REFCLK. The Timer module enable can be selectively generated from either the REFCLK or TIMCLK inputs. This is shown for WDOGCLKEN and TIMER1CLKEN in Figure 2-2.
System Controller and Configuration Logic 2.1.8 System mode control A system mode control state machine is provided to define the source of the system clock and System Controller clock inputs. Note Most applications only use NORMAL mode. The other modes are used for special power down conditions. The state machine is controlled using three mode control bits in the system control register, which define the required system operating mode.
System Controller and Configuration Logic If the nPOR input is activated, the state machine and the required operating mode in the system control register are set to DOZE. If the PRESETn input is activated, the system mode control state machine does not change mode but the required operating mode is set to DOZE in the system control register.
System Controller and Configuration Logic It is possible to override the mode control bits (in the system control register) when an interrupt is generated by the VIC, see Interrupt response mode on page 2-3. The state transitions are shown in Figure 2-3 on page 2-8. The signal states that are required to achieve the modes and transitions shown in Figure 2-3 on page 2-8 are listed in Table 2-1.
System Controller and Configuration Logic DOZE mode In DOZE mode, the system clocks and the System Controller clock are driven from a low frequency oscillator. From DOZE mode it is possible to move into SLEEP mode when none of the mode control bits are set and the processor is in Wait-for-interrupt state. If SLOW mode or NORMAL mode is required the system moves into the XTAL control transition state to initialize the crystal oscillator.
System Controller and Configuration Logic PLL control transition state, PLL CTL PLL control transition state is used to initialize the PLL. In this mode both the systems clock and the System Controller clock are driven from the output of the crystal oscillator. The system moves into the Switch to PLL transition state when either: • the PLL timeout define in the PLL control register expires (when the PLLTIMEEN input is valid) • the PLLON input is set to logic 1.
System Controller and Configuration Logic Core clock control To enable the software to control the relative frequency of the core clock, CLK, and the bus clock, HCLK, the System Controller provides access to the HCLKDIVSEL[2:0] output through the system control register. These output signals are intended for use by the clock generation logic to control the generation of the CLK/HCLK clock source and the HCLKEN input.
System Controller and Configuration Logic 2.2 Clock control The operation of the clock and reset controller is described in the following sections: • Overview • SDRAM interaction with frequency and power modes on page 2-17 • Peripheral clock selection on page 2-18 • Watchdog and Timer module clock enable generation on page 2-4 • PLL frequency control on page 2-6 • System mode control on page 2-7 • System controller registers on page 2-4. 2.2.
System Controller and Configuration Logic An example of external clock sources for the CPU, memory, and bus clocks is shown in Figure 2-5. HCLKEXT ARM926EJ-S Dev.
System Controller and Configuration Logic The clock and reset controller has two modes of operation for driving the processor clocks: • Use the on-chip PLL to de-skew on-chip clocks with respect to the off-chip reference clock XTALCLKEXT. • Drive the on-chip CPUCLK master clock from one of three asynchronous off-chip clocks: REFCLK32K, PLLCLKEXT, or XTALCLKEXT.
System Controller and Configuration Logic In the example shown in Figure 2-5 on page 2-14 and with the default clock and configuration values: • The 24MHz oscillator provides the XTALCLKEXT input clock for the PLL in the ARM926EJ-S Development Chip. • The PLL output CPUCLK is used as the CPU core clock and as the input to the HCLK divider. • HCLK is CPUCLK divided by 1, 2, 3, or 4 depending on the value of CFGHCLKDIVSEL[1:0].
System Controller and Configuration Logic 2.2.2 SDRAM interaction with frequency and power modes The SDRAM refresh period is programmed into the MPMC in HCLK tick units. This setting must be reprogrammed when the operating frequency of the ARM926EJ-S Development Chip changes (when the PLL frequency control is altered or if the system switched operating mode between NORMAL or SLOW).
System Controller and Configuration Logic 2.2.3 Peripheral clock selection The external clock signals are user-defined off-chip clocks. They are gated by the System Controller outputs PERIPHCLKENx. Alternatively, the peripheral clocks may be derived from HCLK. In normal operation the System Controller output PERIPHCTRL0x selects the clock source. To ensure correct operation of the peripheral PERIPHCTRL0x should not change state while the gate is enabled.
System Controller and Configuration Logic 2.3 External configuration signals The configuration block is used to define the operating mode of the chip. It samples the state of HDATAM2[28:0] pads while the rest of the chip is held in reset. The state of these pads can then be held to drive configuration signals within the chip. The operating mode of the chip is then defined when reset is released. Note In a typical device, the configuration signals would be tied HIGH or LOW.
System Controller and Configuration Logic Table 2-3 Configuration signal destinations Signal name Destination Description CFGCPUVINITHI ARM926EJ-S processor VINITHI Determines the reset location of the exception vectors for the ARM926EJ-S processor.When LOW, the vectors are located at 0x0000000. When HIGH, the vectors are located at 0xFFFF0000. The reset value is 0. The value is loaded from HDATAM2[0] during reconfiguration.
System Controller and Configuration Logic Table 2-3 Configuration signal destinations (continued) Signal name Destination Description CFGREMAPDYEXEN ARM926EJ-S Development Chip AMBA infrastructure Dynamic memory and expansion memory alias enable. When HIGH and CFGREMAPSTEXEN is HIGH, then expansion memory is aliased to 0x00000000. Note The combination of CFGREMAPDYEXEN HIGH and CFGREMAPSTEXEN LOW is reserved and must not be used. The reset value is 0.
System Controller and Configuration Logic Table 2-3 Configuration signal destinations (continued) Signal name Destination Description CFGHCLKEXTDIVSEL[2:0] Clock and reset controller Sets the HCLK to HCLKEXT divide ratio. The divide value is set as follows: b000 b001 b010 b011 b100 b101 b110 b111 = = = = = = = = 1 2 3 4 5 6 7 8. The reset value is b001. A new value is loaded from HDATAM2[17:15] during reconfiguration.
System Controller and Configuration Logic Table 2-3 Configuration signal destinations (continued) Signal name Destination Description CFGAHBSASYNC On-chip AHB bridge and clock and reset controller Force the on-chip bridge to asynchronous mode (active HIGH). The reset value is 0. A new value is loaded from HDATAM2[24] during reconfiguration. CFGAHBPASST All AHB bridges Switch the off-chip and on-chip bridges to pass-through mode (active HIGH). The reset value is 0.
System Controller and Configuration Logic ARM926EJ-S Dev.
System Controller and Configuration Logic 2.4 JTAG logic The JTAG interface can control one of two TAP controllers. When nBSTAPEN is LOW the boundary scan TAP controller is selected. The boundary scan TAP controller is a Synopsys DesignWare component. When nBSTAPEN is HIGH the ARM926EJ-S processor TAP controller is selected. This is part of the ARM926EJ-S processor debug features.
System Controller and Configuration Logic nBSTAPENIN ARM926EJ-S Dev. Chip 1 TMSIN SCLK nBSTAPEN TMS DBGTCKEN DBGTMS DBGTDI ARM926EJ-S processor nPOR Multi-ICE synchronization TMS HIGH 0 TCKIN TCK TDIIN TDI RTCKOUT RTCK nTRSTIN nTRST DBGnTDOEN DBGTDO External JTAG interface TCK Boundary Scan TAP controller TDI nTRST 1 HIGH 1 0 0 BSTMSIN 1 BSnTDOEN TDO BSTDOOUT 0 Figure 2-7 JTAG Test Access Port 2-26 Copyright © 2004, 2006 ARM Limited. All rights reserved.
System Controller and Configuration Logic ARM926EJ-S Dev. Chip External signals ARM926EJ-S processor Interface logic DBGTCKEN RTCKOUT TCK Q D RST Q D RST Q D RST DBGTMS TMS Q D EN TDI RST DBGTDI SCLK Q D EN nPOR RST Figure 2-8 Multi-ICE synchronization ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
System Controller and Configuration Logic 2.5 Implementation details for the ARM926EJ-S and system controller The following ARM926EJ-S inputs are tied off: • DBGEN is tied HIGH • DBGDEWPT is tied LOW • DBGEXT[1:0] are tied LOW • DBGIEBRKPT is tied LOW. The following ARM926EJ-S outputs are unconnected: • DBGINSTREXEC • DBGIR[3:0] • DBGRNG[1:0] • DBGRQI • DBGSCREG[4:0] • DBGSDIN • DBGTAPSM[3:0] • STANDBYWFI.
System Controller and Configuration Logic The following system controller inputs are tied off: • PERIPHCLKSTAT[2:0] are tied LOW. • PERIPHCLKSTAT[15:9] are tied LOW. • PERIPHCLKSTAT[31:19] are tied LOW. The following system controller outputs are unconnected: • PERIPHCLKENx[2:0] • PERIPHCLKENx[15:9] • PERIPHCLKENx[31:19] • PERIPHCTRLx[2:0] • PERIPHCTRLx[15:9] • PERIPHCTRLx[31:19] • PLLFREQCTRL[31:9].
System Controller and Configuration Logic 2.6 Control, configuration, and test signals on pads This section lists control, configuration, and test signals on the input/output pads. Note For details on AHB signals, see Chapter 3 Memory Map and Memory Configuration and Chapter 4 AHB Monitor. For details on other peripherals and controllers, see the chapter describing the component. In order to simplify finding signal information, some signals appear in more than one table.
System Controller and Configuration Logic Table 2-6 lists the reset and configuration signals. Table 2-6 Reset and configuration signals Signal Name Type Description nPORESET Input This is an active-LOW power-on reset input used to reset the MPMC refresh timer, System Controller, and the Clock and Reset Controller. CONFIGDATA[28:0] Inputs Configuration inputs on HDATAM2[28:0] sampled at reconfiguration. (See External configuration signals on page 2-19 for details.
System Controller and Configuration Logic Table 2-7 lists the clock signals. Table 2-7 Clock signals Clock Direction Description XTALCLKEXT Input If the on-chip PLL is used, this input is the reference clock for the PLL. If the on-chip PLL is not used, this input can drive the processor and AMBA subsystem clocks. This clock can be selected from the System Controller. PLLCLKEXT Input If the on-chip PLL is not used, this input can drive the processor and AMBA subsystem clocks.
System Controller and Configuration Logic Table 2-7 Clock signals (continued) Clock Direction Description MPMCCLK[4:0] Output These are the output clocks from the MPMC. SMCLK[2:0] Output These are the output clocks from the SSMC. SMFBCLK Input This input is the feedback clock for the SSMC. Table 2-8 lists the JTAG signals. Table 2-8 JTAG TAP signals Signal Name Type Description TCK Input Test clock. TMS Input Test mode select. nTRST Input Test reset (active LOW).
System Controller and Configuration Logic 2-34 Copyright © 2004, 2006 ARM Limited. All rights reserved.
Chapter 3 Memory Map and Memory Configuration This chapter describes the AMBA buses and the memory configuration options. It contains the following sections: • Overview of the AMBA buses in the ARM926EJ-S Development Chip on page 3-2 • Memory map options on page 3-15 • AHB signals to pads on page 3-32. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
Memory Map and Memory Configuration 3.1 Overview of the AMBA buses in the ARM926EJ-S Development Chip The ARM926EJ-S Development Chip bus architecture is described in the following sections: • About the bus architecture • Bus matrix on page 3-3 • AHB restrictions on page 3-6. Note The bus system for the ARM926EJ-S Development Chip is highly configurable. This enables the chip to emulate many different system designs, but it also complicates configuration and use.
Memory Map and Memory Configuration Six AHB buses are provided: ARM I AHB This bus is used by the instruction fetch port of the ARM926EJ-S processor and has access to the memory interfaces. This AHB supports external bus slaves. ARM D AHB This bus is used by the data bus port of the ARM926EJ-S processor and has access to all of the ARM926EJ-S Development Chip peripherals. This AHB supports external bus slaves.
Memory Map and Memory Configuration ETM9 ARM926EJ-S ARM Data AHB ARM Instruction AHB CLCDC AHB DMA1 AHB EXP AHB DMA0 AHB M CLCDC (PL110) config S M M config S DMAC (PL080) VIC (PL190) config S M S M Bus interface S S S S S S config S S AHB Mon.
Memory Map and Memory Configuration The ARM926EJ-S PXP Slave Expansion AHB interfaces that are used have only one peripheral connected to them and the ARM926EJ-S PXP Master Expansion AHB interface has only one master connected to it. Consequently no additional AMBA infrastructure components are required. The ARM Instruction, DMAC 1, DMAC 2 and LCD AHB interfaces from the PXP subsystem are unused.
Memory Map and Memory Configuration 3.1.3 AHB restrictions Using a multilayer AHB system requires that certain restrictions are placed on the use of locked transfers to prevent a deadlock situation. A sequence of locked transfers must all be performed to the same slave in the system. A bus master can ensure this restriction is met by ensuring that a locked sequence of transfers remains inside a 1KB address region.
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Memory Map and Memory Configuration The bridge AHB master output signals drive the pads of the chip through tristate buffers. As the AHB read and write data buses are never active at the same time, the two are combined onto one set of pads. Tristate buffers allow the write data bus to drive the external AHB data bus. The action of the tristate buffers allows multiple AHB masters to drive the off-chip AHB bus under the control of an external arbiter.
Memory Map and Memory Configuration The multiplexor control determines which of the bridge clocking modes is to be used as shown in Table 3-1. Table 3-1 On-chip bridge selection CFGAHBASYNC CFGHCLKEXTDIVSEL[2:0] CFGAHBPASST BRIDGESEL[1:0] Bridge selected 1 xxx x 00 Asynchronous 0 001-111 x 01 Synchronous N:1 0 000 0 10 Synchronous 1:1 0 000 1 11 Pass-through The synchronous 1:1 bridge mode requires that the on-chip and off-chip AHB bus clocks run at the same frequency.
Memory Map and Memory Configuration the bridge are combinatorial. As there are no registers in the AHB signal paths, the bridge will not add any delay to a transaction. This mode is designed for cycle accurate modeling of on-chip masters accessing off-chip slaves. On-chip (slave) bridge This section describes the AHB bridge to on-chip peripherals that forms part of the ARM926EJS PrimeXsys Platform Development Chip multi-layer AHB system.
Memory Map and Memory Configuration The bridge can operate in four modes that define the relationship between the on-chip and off-chip AHB bus clocks and the response of the bridge to AHB transfers. These modes are: • Synchronous 1:1 bridge • Synchronous N:1 bridge • Asynchronous bridge • Pass-through bridge. The synchronous 1:1 bridge mode requires that the on-chip and off-chip AHB bus clocks to run at the same frequency. The bridge is only provided with the on-chip bus clock.
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Memory Map and Memory Configuration 3.1.5 Endianness The ARM926EJ-S Development Chip supports both little-endian and big-endian operation. The endianness required is configured using bit 7 of Register 1 of CP15 in the ARM926EJ-S system control coprocessor. The ARM926EJ-S Development Chip provides the BIGENDOUT output signal so that components outside the ARM926EJ-S Development Chip can also be configured for endianness using this control.
Memory Map and Memory Configuration 3.2 Memory map options Supporting several memory configurations and operating systems requires some configurability of the memory map. CFGBRIDGEMEMMAP This signal defines the memory regions occupied by AHB bridge1 and AHB bridge 2. Accesses to memory regions that are not decoded on-chip are presented to one of the off-chip bridges. If an external device does not acknowledge the request, a bus fault is generated.
Configuration Memory Map and Memory Configuration CFGMPMCnSMC MPMCnSMC CFGBRIDGEMEMMAP CFGBRIDGEMEMMAP CFGREMAPSTEXEN REMAPSTATIC CFGREMAPDYEXEN REMAPMPMCCS5 REMAPEXTERNAL PWP System Controller PWP AMBA AHB infrastructure REMAPCLEAR HIGH HCLK nSYSRST D Q EN nRESE T REMAPSTAT ARM926EJ-S Dev. Chip Figure 3-5 Memory control signals 3-16 Copyright © 2004, 2006 ARM Limited. All rights reserved.
Memory Map and Memory Configuration 3.2.1 TCM The ARM926EJ-S Development Chip contains 32KB of data Tightly Coupled Memory (TCM) and 32KB of instruction TCM. Note Both TCMs operate with one wait state. The TCMs do not support DMA. The caches, TCMs, Memory Management Unit (MMU), and most other system options are controlled using CP15 registers. You can only access CP15 registers with MRC and MCR instructions in a privileged mode.
Memory Map and Memory Configuration Expansion AHB S DMA0 ARM I, LCD & DMA1 ARM D AHB Bridge 1 to Offchip Peripherals AHB Bridge 1 to Offchip Peripherals AHB Bridge 1 to Offchip Peripherals AHB Bridge 1 to Offchip Peripherals MPMC SDRAM MPMCDYCS3 MPMC SDRAM MPMCDYCS2 AHB Bridge 2 to Offchip Peripherals SSMC SSMC nSTATICCS3 nSTATICCS2 nSTATICCS1 nSTATICCS0 nSTATICCS7 nSTATICCS6 nSTATICCS5 nSTATICCS4 MPMCDYCS3 MPMCDYCS2 AHB Bridge 2 to Offchip Peripherals AHB Bridge 2 to Offchip Peripherals S
Memory Map and Memory Configuration The memory map for control signals CFGBRIDGEMEMMAP HIGH and MPMCnSMC HIGH is shown in Figure 3-7. Part of the static memory range has been remapped to a bridge to off-chip peripherals.
Memory Map and Memory Configuration 3.2.4 Bridge remapping The default decoding is to have the AHB M1 selected for accesses between 0x80000000–0xFFFFFFFF and AHB M2 selected for accesses below 0x80000000 that are not decoded by a peripheral in the ARM926EJ-S Development Chip. See Figure 3-8. Figure 3-8 AHB M1 access determined by address range 3-20 Copyright © 2004, 2006 ARM Limited. All rights reserved.
Memory Map and Memory Configuration If CFGBRIDGEMEMMAP is LOW, however, the address decoding for the AHB M1 and AHB M2 buses changes as shown in Figure 3-9. The ARM D master always accesses the AHB M1 bus for regions not decoded by a peripheral in the ARM926EJ-S Development Chip and all other buses access ARM M2 for regions not decoded by a peripheral in the ARM926EJ-S Development Chip.
Memory Map and Memory Configuration Figure 3-10 shows the normal decoding.
Memory Map and Memory Configuration The memory map for bridge remapping is shown in Figure 3-11.
Memory Map and Memory Configuration If the SSMC is not used, part of the static memory range is mapped to an external bridge. The memory map for control signals CFGBRIDGEMEMMAP LOW and MPMCnSMC HIGH is shown in Figure 3-12.
Memory Map and Memory Configuration 3.2.5 AHB memory alias for low memory Normally, fast dynamic memory resides at location 0x00000000. This area is used to store exception vector tables. Address remap functionality is provided to temporarily map an alias of another memory region to 0x00000000–0x03FFFFFF after a power-on reset. The memory map outside the 0x00000000 to 0x03FFFFFF address range is only controlled by MPMCnSMC and CFGBRIDGEMEMMAP.
Memory Map and Memory Configuration Figure 3-14 shows the internal bus map for: • REMAPSTATIC LOW (only dynamic memory in boot area) • MPMCnSMC X • CFGBRIDGEMEMMAP HIGH (AHB M1 determined by address range) • REMAPEXTERNAL LOW (boot memory is controlled by MPMC ).
Memory Map and Memory Configuration Expansion AHB S DMA0 AHB AHB Bridge 2 to Off-chip Peripherals MPMC MPMCDYCS1 AHB Bridge 2 to Off-chip Peripherals ARM I, CLCD & DMA1 AHB ARM D AHB AHB Bridge 2 to Off-chip Peripherals AHB Bridge 2 to Off-chip Peripherals MPMC MPMC MPMCDYCS1 MPMCDYCS1 0x10000000 0x0FFFFFFF MPMC MPMC MPMC MPMCDYCS0 MPMCDYCS0 MPMCDYCS0 SSMC SSMC SSMC nSTATICCS1 nSTATICCS1 nSTATICCS1 0x00000000 Figure 3-15 Alias for REMAPSTATIC HIGH and MPMCnSMC LOW Figure 3-16 sho
Memory Map and Memory Configuration Figure 3-17 shows the internal bus map for: • REMAPSTATIC HIGH • MPMCnSMC HIGH (the MPMC controls static memory) • CFGBRIDGEMEMMAP HIGH (AHB M1 access selected by address range) • REMAPEXTERNAL HIGH (boot memory is controlled off-chip).
Memory Map and Memory Configuration 3.2.6 APB address maps Figure 3-19 shows the Core APB and DMA APB memory organization.
Memory Map and Memory Configuration The DMA APB address map is listed in Table 3-1. The DMA APB is not accessible by the ARM I, CLCD, or DMA1 masters. Accesses from these masters are routed to an off-chip bridge. Table 3-1 DMA APB peripheral base addresses Base address Base name Peripheral 0x101F4000 SSP Synchronous Serial Port 0x101F3000 UART2 UART two 0x101F2000 UART1 UART one 0x101F1000 UART0 UART zero 0x101F0000 SCI Smart Card Interface The Core APB address map is listed in Table 3-2.
Memory Map and Memory Configuration 3.2.7 MBX memory map The mapping of the internal MBX AHB bus to dynamic memory is shown in Figure 3-20.
Memory Map and Memory Configuration 3.3 AHB signals to pads This section describes the AHB signals on the input/output pads. Note The HDATAM2[28:0] signals on the AHB M2 bus are also used for the configuration signals CFGDATA[28:0], see External configuration signals on page 2-19. Table 3-1 AHB M1 signals Signal Name Type Description HBUSREQM1 Output Bus request. A signal from the master to the arbiter, which indicates that the master interface requires the bus.
Memory Map and Memory Configuration Table 3-1 AHB M1 signals (continued) Signal Name Type Description HRESPM1[1:0] Input The transfer response provides additional information on the status of a transfer. Two different responses are provided, OKAY and ERROR. HDATAM1[31:0] Bidirectional Read/write data bus. HCLKM1 Input Asynchronous AHB bus clock from an external source. Table 3-2 AHB M2 signals Signal Name Type Description HBUSREQM2 Output Bus request.
Memory Map and Memory Configuration Table 3-2 AHB M2 signals (continued) Signal Name Type Description HRESPM2[1:0] Input The transfer response provides additional information on the status of a transfer. Two different responses are provided, OKAY and ERROR. HDATAM2[31:0] Bidirectional Read/write data bus. HCLKM2 Input Asynchronous AHB bus clock from an external source. Table 3-3 AHB S signals Signal Name Type Description HMASTLOCKS Input Master lock signal.
Part B Controllers and Peripherals
Chapter 4 AHB Monitor This chapter describes the AHB Monitor in the ARM926EJ-S Development Chip. It contains the following section: • About the AHB monitor on page 4-2 • Functional description on page 4-3 • AHB Monitor signals on pads on page 4-42. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
AHB Monitor 4.1 About the AHB monitor The ARM926EJ-S Development Chip contains a multi-layer AHB system to provide high bandwidth connectivity between the various bus masters and slaves both within and outside the ARM926EJ-S Development Chip. The AHB Monitor connects to the AHB matrix. A slave bus is available for reading bus activity counters. The release version for the AHB Monitor is SP816. The base address for the AHB registers is 0x101D000.
AHB Monitor 4.2 Functional description The AHB monitor interface is shown in Figure 4-1. ARM926EJ-S Dev. Chip AHB monitor ARM D layer signals ARM I layer signals DMA 0 layer signals DMA 1 layer signals CLCDC layer signals Bus matrix Layer monitors AHBMONITOR[33:0] Expansion layer signals MBX GXI signals AHB control and configuration Register interface Figure 4-1 AHB monitor block diagram The base address of the AHB monitor is at 0x101D0000–0x101DFFFF. 4.2.
AHB Monitor AHB Monitor packet format There are 33 bits per data packet. To simplify the subsequent analysis of the data, there are completely separate groups of bits associated with each AHB layer and the GXI. The packet can be viewed as seven independent subpackets as shown in Figure 4-2. There are six bits assigned to the ARM-D layer, five to each of the DMA and Expansion layers, and four for the LCD, ARM-I and GXI layers.
AHB Monitor The total number of different NRs and NWs states, that are valid, is dependent upon the layer - some masters only perform reads and most have connections to only a subset of the possible slaves. Similarly the number of valid Sb states is dependent upon the layer because most masters are not capable of producing all possible burst types. For these reasons, the format of the encoded signals has been developed to allow the bit allocation per layer as stated in the previous section.
AHB Monitor Table 4-2 Sample output (continued) Pattern on bus Description WS Third read transfer from slave 2 in a wrapping burst of 4, one wait state inserted by the slave S_WRAP4 - WS Fourth read transfer from slave 2 in a wrapping burst of 4, one wait state inserted by the slave S_WRAP4 - AHB Cycle State encoding Table 4-3 shows the bit pattern encoding used for each of the possible Bus Cycle States on each layer and shows which of those values can actually be generated by that layer (boxes m
AHB Monitor Table 4-3 Bus state bit patterns (continued) Symbol and bus state [5] [4] a b S_INCR16, Sequential_INCR16 0 NR_EXP1, Expansion Bridge 1 [3:0] ARM-D [28:23] ARM-I [22:19] DMA-0 [18:14] DMA-1 [13:9] EXP [8:4] LCD [3:0] 0 0111 - - Y Y Y Y 0 0 1000 Y Y Y Y Y Y NR_EXP2, Expansion Bridge 2 0 0 1001 Y Y Y Y Y Y NR_MPMC, MPMC 0 0 1010 Y Y - Y Y Y NR_SMC, SMC 0 0 1011 Y Y - Y Y Y WS, Wait_Slave 0 0 1100 Y Y Y Y Y Y WB, Wait_Bus 0
AHB Monitor Table 4-3 Bus state bit patterns (continued) [5] [4] a b NR_APBCore, APB bridge to Core peripherals 0 NR_AHBMON, AHB Monitor registers [3:0] ARM-D [28:23] ARM-I [22:19] DMA-0 [18:14] DMA-1 [13:9] EXP [8:4] LCD [3:0] 1 1101 Y - - - Y - 0 1 1110 Y - - - Y - HRESET 0 1 1111 - - Y Y Y - 0x20- 0x2F, Unused 1 0 xxxx - - - - - - NW_SMCCFG, SMC 1 1 0111 Y - - - - - NW_MPMCCFG, MPMC config registers 1 1 0000 Y - - - - - NW_VIC, VIC r
AHB Monitor GXI Cycle States and Encoding The GXI can perform concurrent read and write activities due to the split transfer architecture it employs. Therefore, the four debug output pins related to the GXI are divided into two, providing separate state information for the read and write channels. The four bits dedicated to the GXI assign the upper two bits to the read channel and the lower bits to the write channel, AHBMONITOR[32:29] = {ReadState, WriteState}.
AHB Monitor Table 4-5 Bit patterns for GXI state for address channel 4.2.
AHB Monitor Accessing the Profiling Counters The profiling counters of each layer are accessed through an AHB slave port. They are only connected to the ARM-D and EXPansion bus layers at a base address of 0x101D0000. The control and configuration registers for the profiling counter are also accessible through this base address. Each register in the AHB monitor is word aligned.
AHB Monitor As the AMBA AHB specification allows for divergent behavior in reaction to the ERROR specification, the behavior of each of the AHB masters contained within the ARM926EJ-S Development Chip design is shown below to help you understand the profile information collected on each layer: CLCDC It stops the current burst by issuing a bus idle and enters an error state that issues an interrupt signal. Once the interrupt is cleared the controller begins the frame again.
AHB Monitor Counted events on ARM-I layer The ARM926EJ-S ARM-I BIU performs only a small subset of AHB transfer types. It performs no writes at all. All reads are word-sized, even when not in ARM state. For example, two half-word Thumb instructions are fetched by one word transfer. It performs only burst types SINGLE, INCR4, WRAP8 (I-cache line fills). There are no BUSY transfers on this layer. Table 4-6 shows all the events that are recorded on the ARM-I layer.
AHB Monitor Counted events on CLCDC layer The PrimeCell PL110 CLCDC BIU performs only a small subset of AHB transfer types: • it performs no writes at all • all reads are word-sized • it performs only burst types INCR, INCR4, INCR8, and INCR16 • the unspecified length bursts are used to implement single transfers by the CLCDC. There are no BUSY transfers on this layer, because the FIFO in this particular implementation is synthesized from flip-flops rather than using a compiled RAM block.
AHB Monitor Counted events on DMA-0 layer The PrimeCell PL080 DMAC BIU can perform all active AHB transfer types, that is, reads and writes of size 8, 16, and 32-bits. It performs only burst types INCR, INCR4, INCR8, and INCR16. DMA master number 0 is used to access the three DMA-capable peripherals within the ARM926EJ-S Development Chip (UART, SCI, SSP) or external slaves accessed through the off-chip bridges. The APB bridge generates the PSEL signal from a direct binary decode of HADDR[15:12].
AHB Monitor Table 4-8 DMA 0 events (continued) Counter Name Description CtDma0WaitNonSeqSlave Number of wait states on the first transfer of a burst that were caused by a slave CtDma0WaitNonSeqBus Number of wait states on the first transfer of a burst that were caused by the bus infrastructure CtDma0WaitThresholdHit Number of occurrences that a wait-state exceeded a configurable threshold Counted events on DMA-1 layer The PrimeCell PL080 DMAC BIU can perform all active AHB transfer types, that is,
AHB Monitor Table 4-9 DMA 1 events (continued) Counter Name Description CtDma1WaitNonSeqSlave Number of wait states on the first transfer of a burst that were caused by a slave CtDma1WaitNonSeqBus Number of wait states on the first transfer of a burst that were caused by the bus infrastructure CtDma1WaitThresholdHit Number of occurrences that a wait-state exceeded a configurable threshold Counted events on EXPansion layer The expansion layer is connected to an AHB-AHB bridge to enable external AHB
AHB Monitor Table 4-10 EXP layer events (continued) Counter Name Description CtExpBurstWrap4 Number of 4-beat wrapping bursts CtExpBurstIncr4 Number of 4-beat incrementing bursts CtExpBurstWrap8 Number of 8-beat wrapping bursts CtExpBurstIncr8 Number of 8-beat incrementing bursts CtExpBurstWrap16 Number of 16-beat wrapping bursts CtExpBurstIncr16 Number of 16-beat incrementing bursts CtExpWaitTotal Total number of wait states CtExpWaitNonSeqSlave Number of wait states on the first transfer
AHB Monitor disables the counters during cycles that the DBGACK is asserted. All counters can be reset by writing to the AHBMONRstCntrs register, and preset to their absolute address by writing to the AHBMONPrstCntrs register.
AHB Monitor Table 4-11 D layer events (continued) 4-20 Event Counter Name Description CtArmdPageWalkD Number of read transfers for D-side page table walks, that is, CtArmdRdBurstSingProtCBPD - number of single word reads with particular HPROT. CtArmdPageWalkI Number of read transfers for I-side page table walk reads ,that is, CtArmdRdBurstSingProtCBPI - number of single word reads with particular HPROT.
AHB Monitor Counted Events on the MBX GXI Layer The MBX connects to the MPMC through a dedicated interconnect. The connection performs single unit read and write transfers over logically disjoint data buses. Further details of the interconnect are contained with the MBX TRM. Table 4-12 shows all the events that are recorded on the MBX GXI bus. These counters are enabled through the counter enable bit in the AHBMONCtrlReg.
AHB Monitor Miscellaneous Counted Events with the AHB Monitor Table 4-13 presents three additional counters included to enable the further evaluation of the system based on the number of cycles elapsed dependent on certain operating conditions. With exception of the CtTotalCycles, these counters are enabled through the counter enable bit in the AHBMONCtrlReg register (see AHBMONCtrlReg on page 4-39). The CtTotalCyclesNonDebug counter is controlled also by the DBGACK and when the track DBGACK is asserted.
AHB Monitor 4.3 AHB Monitor registers Many of the registers in the AHB monitor replicate behavior over two or more PWP AHB layers. Therefore to minimize verboseness, the behaviors of the registers that overlap are described together.
AHB Monitor Table 4-14 AHB Monitor registers Name Address Description CtArmiRd 0x101D0000 Counter. See CtRd on page 4-29. CtArmiBurstSingle 0x101D0008 Counter. See CtBurstSingle on page 4-30. CtArmiBurstIncr4 0x101D0014 Counter. See CtBurstIncr4 on page 4-31. CtArmiLineFill 0x101D0040 Counter. See CtArmLineFill on page 4-33. CtArmiWaitTotal 0x101D0030 Counter. See CtWaitTotal on page 4-34. CtArmiWaitNonSeqSlave 0x101D0028 Counter.
AHB Monitor Table 4-14 AHB Monitor registers (continued) Name Address Description CtDma0WrSci 0x101D024C Counter. See CtWr on page 4-30. CtDma0RdSsp 0x101D0250 Counter. See CtRd on page 4-29. CtDma0WrSsp 0x101D0254 Counter. See CtWr on page 4-30. CtDma0BurstIncr 0x101D020C Counter. See CtBurstIncr on page 4-31. CtDma0BurstIncr4 0x101D0214 Counter. See CtBurstIncr4 on page 4-31. CtDma0BurstIncr8 0x101D021C Counter.
AHB Monitor Table 4-14 AHB Monitor registers (continued) Name Address Description CtExpWr 0x101D0404 Counter. See CtWr on page 4-29. CtExpRdApbDma 0x101D0454 Counter. See CtRd on page 4-29. CtExpWrApbDma 0x101D0458 Counter. See CtWr on page 4-30. CtExpRdApbCore 0x101D045C Counter. See CtRd on page 4-29. CtExpWrApbCore 0x101D0460 Counter. See CtWr on page 4-30. CtExpBurstSingle 0x101D0408 Counter. See CtBurstSingle on page 4-30.
AHB Monitor Table 4-14 AHB Monitor registers (continued) Name Address Description CtArmdBurstSingle 0x101D0508 Counter. See CtBurstSingle on page 4-30. CtArmdBurstIncr4 0x101D0514 Counter. See CtBurstIncr4 on page 4-31. CtArmdBurstIncr8 0x101D051C Counter. See CtBurstIncr8 on page 4-32. CtArmdLineFill 0x101D0540 Counter. See CtArmLineFill on page 4-33. CtArmdCastOut4 0x101D0544 Counter. See CtArmdCastOut on page 4-33. CtArmdCastOut8 0x101D0548 Counter.
AHB Monitor Table 4-14 AHB Monitor registers (continued) Name Address Description CtGxiRdDWaitThreshold 0x101D0638 4-bit wide R/W Wait Threshold Register. See CtRd on page 4-29. CtGxiPageChange 0x101D0608 Counter. See CtGxiPageChange on page 4-38. CtGxiPageSize 0x101D0E08 2-bit Read-only register that selects page size used by the page change counter. See GxiPageSize on page 4-38. CtTotalCycles 0x101D0700 Value of a counter of bus cycles. See CtTotalCycles on page 4-39.
AHB Monitor 4.3.1 CtRd There are six read count registers. Each is associated with a specific AHB layer: CtArmdRd • • CtArmiRd • CtDma0Rd • CtDma1Rd • CtClcdRd • CtExpRd. The registers contain the total count of completed read transfers of all possible burst types that have occurred on the associated AHB layer. The count is disabled by default and can be controlled through the AHBMONCtrlReg, and reset through the AHBMONRstCtrs.
AHB Monitor These registers contain the total count of completed read transfers of all possible burst types that have occurred on the DMA-0 AHB layer that have accessed a specific APB slave. The count is disabled by default and can be controlled through the AHBMONCtrlReg, and reset through the AHBMONRstCtrs. The counters associated with the ARM D layer are also controlled by DBGACK in relation to configuration, see AHBMONCtrlReg on page 4-39. 4.3.
AHB Monitor 4.3.6 CtBurstIncr The read count registers are associated with a specific AHB layer that contains a master that is capable of this burst format. CtDma0BurstIncr • • CtDma1BurstIncr • CtClcdBurstIncr • CtExpBurstIncr. These registers contain the total count, read + write, of completed unspecified length burst transfers that have occurred on the associated AHB layer. The count is disabled by default and can be controlled through the AHBMONCtrlReg, and reset through the AHBMONRstCtrs. 4.
AHB Monitor 4.3.9 CtExpBurstWrap8 Only the EXPansion bus contains a master that is capable of issuing a WRAP8 burst transfer that is referred to by the burst name, namely the AHB-AHB bridge, which interfaces external AHB master components to the PWP environment. The ARM926PXP also performs WRAP8 burst transfers, but the counts are referred by the associated activity of a cache line fill.
AHB Monitor 4.3.12 CtBurstIncr16 The INCR16 burst count registers are associated with a specific AHB layer that contains a master that is capable of this burst format: CtDma0BurstIncr16 • • CtDma1BurstIncr16 • CtClcdBurstIncr16 • CtExpBurstIncr16. These registers contain the total count, read + write, of completed INCR16 burst transfers that have occurred on the associated AHB layer.
AHB Monitor 4.3.15 CtArmdPageWalk The ARM926 data AHB interface uses the SINGLE burst format with a specific protection bits set to perform page table walks for either the instruction or data path: CtArmdPageWalkD • • CtArmdPageWalkI. These registers contain the total count of completed page table walk transactions that have occurred on the ARM-D AHB layer for the Instruction or Data path.
AHB Monitor reset through the AHBMONRstCtrs. The counters associated with the ARM D and ARM I layers are also controlled by the DBGACK in relation to configuration, see AHBMONCtrlReg on page 4-39. 4.3.18 CtWaitNonSeqBus The NONSEQ bus wait count registers are associated with a specific AHB layer: • CtArmdWaitNonSeqBus • CtArmiWaitNonSeqBus • CtDma0WaitNonSeqBus • CtDma1WaitNonSeqBus • CtClcdWaitNonSeqBus • CtExpWaitNonSeqBus.
AHB Monitor 4.3.20 WaitThreshold register The eight WaitThresholdHit registers are associated with a specific AHB layer: ArmdWaitThreshold • • ArmiWaitThreshold • Dma0WaitThreshold • Dma1WaitThreshold • ClcdWaitThreshold • GxiRdAWaitThreshold • GxiRdDWaitThreshold • GxiWrAWaitThreshold. Table 4-1 WaitThreshold 4.3.21 Bits Name Type Function [31:4] - - Reserved, read undefined, must be written to with zeros.
AHB Monitor 4.3.22 CtGxiRd The MBX GXI performs a read transfer completely disjoint from the address cycle. Transfer requests are acknowledged in the address cycle with the GAREADY signal, and transfers are completed in subsequent cycles, which are acknowledged by the GDREADY signal. The MBX initiates a read transfer request by driving GWRITE LOW and GTRANS HIGH. This register contains the total count of completed read transfers that have occurred on the MBX GXI Bus.
AHB Monitor 4.3.25 CtGxiPageChange The MBX transfers are limited to single word transactions. Page changes are tracked to monitor the behavior of the memory interface of the MBX. Contains the total count of transfers that causes a page change from the previous transfer. The page size is set by the GxiPageSize register. The count is disabled by default and can be controlled through the AHBMONCtrlReg, and reset through the AHBMONRstCtrs. 4.3.
AHB Monitor 4.3.29 AHBMONCtrlReg The AHB Monitor disables all the event counters at reset, but enables the Debug output. For normal device operation the information produced by the AHB Monitor is not required. AHBMONCtrlReg was included to enable or disable the AHB monitor module. The Track DBGACK bit was included to provide method of discounting bus activity caused by the processor operating in debug mode.
AHB Monitor 4.3.33 AHBMONPeriphID 0 to 3 Bits [7:0] of the four AHBMONPeriphID[3:0] registers form a conceptual 32-bit register that provides a method of identification and version information for the AHB Monitor as shown in Figure 4-3. The bit ranges are shown in Table 4-1.
AHB Monitor 4.3.34 AHBMONPCellID Bits [7:0] of the four AHBMONPCellID[3:0] registers form a conceptual 32-bit register that is used as a standard cross-peripheral identification system as shown in Figure 4-4. It is set at the value of 0xB105F00D.
AHB Monitor 4.4 AHB Monitor signals on pads The output signals are shown in Table 4-1. Table 4-1 Output pad signal descriptions 4-42 Name Description AHBMONITOR[32:29] GXI bus subpacket AHBMONITOR[28:23] ARM data bus subpacket AHBMONITOR[22:19] ARM instruction bus subpacket AHBMONITOR[18:14] DMA 0 bus subpacket AHBMONITOR[13:9] DMA 1 bus subpacket AHBMONITOR[8:4] Expansion bus subpacket AHBMONITOR[3:0] LCD bus subpacket Copyright © 2004, 2006 ARM Limited. All rights reserved.
Chapter 5 Color LCD Controller (CLCDC) This chapter describes the display controller in the ARM926EJ-S Development Chip. It contains the following sections: • About the CLCDC on page 5-2 • Functional description on page 5-4 • CLCD signals on pads on page 5-31. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
Color LCD Controller (CLCDC) 5.1 About the CLCDC The PrimeCell Smart Color LCD Controller PL110 (CLCDC) is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-a-Chip (SoC) peripheral that is developed, tested, and licensed by ARM. The CLCDC connects to the AHB bus matrix. The release version used is PL110 CLCDC r0p0-00alp0. For detailed information on the controller, see the ARM PrimeCell Color LCD Controller (PL110) Technical Reference Manual.
Color LCD Controller (CLCDC) Besides data formatting, the CLCDC provides a set of programmable display control signals, that include: • LCD panel power enable • pixel clock • horizontal and vertical synchronization pulses • display bias. The CLCDC uses the external clock source CLCDCLKEXT for timing the pixel clock. The CLCDC data output can be converted to a VGA display signal by adding an external Digital to Analog Converter (DAC).
Color LCD Controller (CLCDC) 5.2 Functional description Simplified block diagrams of the CLCDC and the external interface are shown in Figure 5-1 and Figure 5-2 on page 5-5.
Color LCD Controller (CLCDC) Bus matrix PL110 CLCDC ARM926EJ-S Dev. Chip CLCDOUT[23:0] CLCD[23:0] CLPOWEROUT CLPOWER Panel data Panel enable CLLPOUT CLLP Line sync CLCPOUT CLCP Panel clock CLFPOUT CLFP Vertical sync CLACOUT CLAC Data enable CLLEOUT CLLE Clock and reset controller CLCDCLKEXT Line end Reference clock DMA and interrupt Figure 5-2 CLCDC block diagram ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
Color LCD Controller (CLCDC) 5.2.1 Registers The base address of the ARM PrimeCell CLCDC is 0x10120000. The following locations are reserved, and must not be used during normal operation: • locations 0x10120050–0x101201FC are reserved for possible future extensions • locations 0x10120400–0x101207FF are reserved for test purposes • locations 0x10120C30–0x10120FDC are reserved for possible future extensions.
Color LCD Controller (CLCDC) 5.3 Hardware cursor extension to PL110 The PL110 controller in the ARM926EJ-S Development Chip has been extended to include a hardware cursor extension. 5.3.1 Hardware cursor extension Before the hardware cursor was introduced, moving the cursor required software to: • save an image of the area under the next cursor position • update the area with the cursor image • repair the last cursor position with a previously saved image.
Color LCD Controller (CLCDC) Operation All cursor programming registers are accessed through the CLCDC slave interface. The cursor image is held in the CLCDC in a 256x32-bit dual-port RAM.
Color LCD Controller (CLCDC) Movement The following descriptions assume that both the screen and cursor origins are at the top left of the visible screen (the first visible pixel scanned each frame). Each pixel coordinate is assumed to be the top left corner of the pixel as shown in Figure 5-4. (0,0) ClcdCrsrXY(X) ClcdCrsrXY(Y) Figure 5-4 Hardware cursor movement The ClcdCrsrXY Register controls the cursor position on the cursor overlay. This provides separate fields for X and Y ordinates.
Color LCD Controller (CLCDC) Because the ClcdCrsrXY Register values are positive integers, to emulate cursor clipping on the left and top of screen, a Clip Index Register, ClcdCrsrClipXY, is provided. This determines which point of the cursor image is positioned at the ClcdCrsrXY coordinate. For clipping functions on the Y axis, ClcdCrsrXY(X) is zero, and Clip(X) is programmed to provide the offset into the cursor image (X2 and X3).
Color LCD Controller (CLCDC) Image format The LCD frame buffer supports three packing formats, but the hardware cursor image requirement has been simplified to support only LBBP. This is little-endian byte, big-endian pixel for Windows CE mode. The Image RAM start address (IBase) is 0x10120800. The displayed cursor coordinate system is expressed in terms of (X,Y). 64x64 is an extension of the 32x32 format shown in Figure 5-6.
Color LCD Controller (CLCDC) For 32x32 bit pixels, four cursors are held in memory, each with the same pixel format. Table 5-3 lists the base addresses for the four cursors. Table 5-3 32x32 cursor base addresses Address Description 0x10120800 Cursor0 start address 0x10120900 Cursor1 start address 0x10120A00 Cursor2 start address 0x10120B00 Cursor3 start address Table 5-4 and Table 5-5 on page 5-13 list the LBBP buffer to pixel mapping for Cursor0.
Color LCD Controller (CLCDC) Table 5-5 LBBP buffer to pixel mapping 32x32 Cursor0 for datawords [15:0] Offset from CLCDC base at 0x10120800 Dataword [15:14] [13:12] []11:10] [9:8] [7:6] [5:4] [3:2] [1:0] +0 (4,0) (5,0) (6,0) (7,0) (0,0) (1,0) (2,0) (3,0) +4 (20,0) (21,0) (22,0) (23,0) (16,0) (17,0) (18,0) (19,0) +(8*y) (4,y) (5,y) (6,y) (7,y) (0,y) (1,y) (2,y) (3,y) +(8*y)+4 (20,y) (21,y) (22,y) (23,y) (16,y) (17,y) (18,y) (19,y) +0xF8 (4,31) (5,31) (6,31) (
Color LCD Controller (CLCDC) Table 5-7 LBBP buffer to pixel mapping 64x64 for datawords [15:0] Offset from CLCDC base at 0x10120800 Dataword [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] +0 (4,0) (5,0) (6,0) (7,0) (0,0) (1,0) (2,0) (3,0) +0x4 (20,0) (21,0) (22,0) (23,0) (16,0) (17,0) (18,0) (19,0) +0x8 (36,0) (37,0) (38,0) (39,0) (32,0) (33,0) (34,0) (35,0) +0xC (52,0) (53,0) (54,0) (55,0) (48,0) (49,0) (50,0) (51,0) +16*y+0 (4,y) (5,y) (6,y) (7,y)
Color LCD Controller (CLCDC) Table 5-8 32x32 software mask storage Data bit to pixel correspondence External memory offset [7] [6] [5] [4] [3] [2] [1] [0] +0 (0,0) (1,0) (2,0) (3,0) (4,0) (5,0) (6,0) (7,0) +1 (8,0) (9,0) (10,0) (11,0) (12,0) (13,0) (14,0) (15,0) +2 (16,0) (17,0) (18,0) (19,0) (20,0) (21,0) (22,0) (23,0) +3 (24,0) (25,0) (26,0) (27,0) (28,0) (29,0) (30,0) (31,0) . . .
Color LCD Controller (CLCDC) Pixel encoding Each pixel of the cursor requires two bits of information that are interpreted as Color0, Color1, Transparent, and Transparent inverted. In the coding scheme, bit 1 selects between color and transparent (AND mask) and bit 0 selects variant (XOR mask). Table 5-10 lists the pixel encoding bit assignments. Table 5-10 Pixel encoding 5-16 Bits Description [00] Color0.
Color LCD Controller (CLCDC) 5.3.2 Hardware cursor registers Table 5-1 lists the hardware cursor registers.
Color LCD Controller (CLCDC) Cursor Image RAM Register The CursorImage Register is read and write. It contains 256-word wide values which are used to define the image or images overlaid by the hardware cursor mechanism. The image must always be stored in LBBP mode (little-endian byte, big-endian pixel) mode, as described in Image format on page 5-11. Two bits are used to encode color and transparency for each pixel in the cursor.
Color LCD Controller (CLCDC) Table 5-2 lists the register bit assignments. Table 5-2 ClcdCrsrCtrl Register bit assignments Bit Name Function [31:6] - Reserved, read undefined, do not modify. [5:4] CrsrNumber[1:0] Cursor Image number. This field provides an offset into the cursor image buffer, to enable one of four 32x32 cursors to be addressed.
Color LCD Controller (CLCDC) Cursor Configuration Register The ClcdCrsrConfig Register is read and write. It provides overall configuration information for the hardware cursor. Figure 5-8 shows the register bit assignments. 31 2 1 0 Undefined CrsrFrameSync CrsrSize Figure 5-8 ClcdCrsrConfig Register bit assignments Table 5-3 lists the register bit assignments.
Color LCD Controller (CLCDC) Figure 5-9 shows the register bit assignments. 31 24 23 Undefined 16 15 Blue 8 7 Green 0 Red Figure 5-9 ClcdCrsrPalette0 and ClcdCrsrPalette1 Register bit assignments Table 5-4 lists the register bit assignments.
Color LCD Controller (CLCDC) Table 5-5 lists the register bit assignments. Table 5-5 ClcdCrsrXY Register bit assignments Bit Name Function [31:28] - Reserved, read undefined, do not modify. [27:26] CrsrY (expansion) Reserved for coordinate expansion. Must be written as zero. [25:16] CrsrY Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display. [15:12] - Reserved, read undefined, do not modify.
Color LCD Controller (CLCDC) Table 5-6 lists the register bit assignments. Table 5-6 ClcdCrsrClip Register bit assignments Bit Name Function [31:14] - Reserved, read undefined, do not modify. [13:8] CrsrClipY Distance from top of cursor image to the first displayed pixel in cursor. When 0, the first displayed pixel is from the top line of the cursor image. [7:6] - Reserved, read undefined, do not modify.
Color LCD Controller (CLCDC) Table 5-7 lists the register bit assignments. Table 5-7 ClcdCrsrIMSC Register bit assignments Bit Name Function [31:1] - Reserved, read undefined, do not modify. [0] CrsrIM When set, the cursor interrupts the processor immediately after reading of the last word of cursor image. When clear, the cursor never interrupts the processor. Cursor Interrupt Clear Register The ClcdCrsrICR Register is write-only.
Color LCD Controller (CLCDC) Cursor Raw Interrupt Status Register The ClcdCrsrRIS Register is read-only. It is set to indicate a cursor interrupt, and, when enabled, controls the state of the interrupt signal to the system interrupt controller. Note The ClcdCrsrRIS Register is valid regardless of the state of the CrsrIMSC bit. Figure 5-14 shows the register bit assignments. 31 1 0 Undefined CrsrRIS Figure 5-14 ClcdCrsrRIS Register bit assignments Table 5-9 lists the register bit assignments.
Color LCD Controller (CLCDC) Cursor Masked Interrupt Status Register The ClcdCrsrMIS Register is read-only. It is set to indicate a cursor interrupt providing that the interrupt bit is not masked. Figure 5-15 shows the register bit assignments. 31 1 0 Undefined CrsrMIS Figure 5-15 ClcdCrsrMIS Register bit assignments Table 5-10 lists the register bit assignments. Table 5-10 ClcdCrsrMIS Register bit assignments 5-26 Bit Name Function [31:1] - Reserved, read undefined.
Color LCD Controller (CLCDC) Peripheral Identification Registers The CLCDPeriphID0-3 Registers are four 8-bit read-only registers that span address locations 0xFE0-0xFEC. The registers can conceptually be treated as a single 32-bit register. The registers provide the peripheral options listed in Table 5-11. Table 5-11 Peripheral Identification Register options Bit Function PartNumber[11:0] Identifies the peripheral. The three-digit product code 0x11 is used. DesignerID[19:12] Identifies the designer.
Color LCD Controller (CLCDC) The CLCDPeriphID0 Register is read-only. It is hard-coded and the fields in the register determine the reset value. Table 5-12 lists the register bit assignments. Table 5-12 CLCDPeriphID0 Register bit assignments Bit Name Function [31:8] Reserved Reserved, read undefined [7:0] PartNumber0 These bits read back as 0x11 The CLCDPeriphID1 Register is read-only. It is hard-coded and the fields in the register determine the reset value.
Color LCD Controller (CLCDC) PrimeCell Identification Registers The CLCDPCellID0-3 Registers are four 8-bit read-only registers that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a single 32-bit register. The register is used as a standard cross-peripheral identification system. Figure 5-17 shows the register bit assignments.
Color LCD Controller (CLCDC) The CLCDPCellID2 Register is read-only. It is hard-coded and the fields in the register determine the reset value. Table 5-18 lists the register bit assignments. Table 5-18 CLCDPCellID2 Register bit assignments Bit Name Function [31:8] Reserved Reserved, read undefined [7:0] CLCDPCellID2 These bits read back as 0x05 The CLCDPCellID3 Register is read-only. It is hard-coded and the fields in the register determine the reset value.
Color LCD Controller (CLCDC) 5.4 CLCD signals on pads The only external input signal to the CLCDC is the external clock signal CLCDCLKEXT. Table 5-20 lists the output interface signals.
Color LCD Controller (CLCDC) 5-32 Copyright © 2004, 2006 ARM Limited. All rights reserved.
Chapter 6 MOVE Coprocessor This chapter describes the MOVE graphic coprocessor in the ARM926EJ-S Development Chip. It contains the following section: • About the MOVE Coprocessor on page 6-2. Note Details of the MOVE coprocessor function are only available to licensees. Contact ARM for information on licensing. The release version used is MOVE r3p0-00bet0. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
MOVE Coprocessor 6.1 About the MOVE Coprocessor The MOVE coprocessor is a video encoding acceleration coprocessor designed to accelerate Motion Estimation (ME) algorithms within block-based video encoding schemes such as MPEG4 and H.263. This is done by providing support for the execution of Sum of Absolute Differences (SAD) calculations, which account for most of the processing activity within an ME algorithm.
MOVE Coprocessor MOVE coprocessor Control logic CPINSTR Register bank Coprocessor CPDOUT control Data path CPDIN ARM926 coprocessor interface Figure 6-1 MOVE overview ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
MOVE Coprocessor 6-4 Copyright © 2004, 2006 ARM Limited. All rights reserved.
Chapter 7 MBX HR-S Graphics Accelerator This chapter describes the ARM MBX HR-S Graphics Accelerator present in the ARM926EJ-S Development Chip. It contains the following sections: • About the ARM MBX HR-S on page 7-2 • Memory map and registers on page 7-6. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
MBX HR-S Graphics Accelerator 7.1 About the ARM MBX HR-S The ARM MBX HR-S is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-a-Chip (SoC) component. Figure 7-1 shows a top-level block diagram of the ARM MBX HR-S. The MBX component connects directly to the MPMC and the AHB bus matrix.
MBX HR-S Graphics Accelerator The ARM MBX HR-S operates on 3D scene data (sent as batches of triangles) that are transformed and lit either by the Central Processing Unit (CPU) or by the VGP. Triangles are written directly to the TA on a First In First Out (FIFO) basis so that the CPU is not stalled. The TA performs advanced culling on triangle data by writing the tiled non-culled triangles to the external memory.
MBX HR-S Graphics Accelerator 7.1.
MBX HR-S Graphics Accelerator 7.1.2 Functional overview PowerVR technology is implemented as a display list renderer. Groups of polygons are batched together into a display list before being processed by the 3D rendering hardware. This is fundamentally different to the approach used by conventional systems, because it enables a scene to be partitioned into small tiles or regions, each of which is rendered independently.
MBX HR-S Graphics Accelerator 7.2 Memory map and registers The MBX HR-S memory map is described in the following sections: • MBX HR-S registers • AHB slave interface • GX port memory interface on page 7-7. 7.2.1 MBX HR-S registers The MBX control registers are located starting at memory location 0x140000000. For detailed information on the MBX registers, see the ARM MBX HR-S Graphics Core Technical Reference Manual. 7.2.
MBX HR-S Graphics Accelerator 7.2.3 GX port memory interface The MBX HR-S contains an MMU that maps the 8192 4KB pages making up the 32MB linear address space of the MBX into 4KB (potentially) fragmented pages in the 4GB system memory space. Translation is performed using a table with 8KB entries, one for each 4KB page in a 32MB linear address space. Each entry is a word, so 32KB must be allocated for the translation table. Table entries are byte-aligned.
MBX HR-S Graphics Accelerator Linear local word address.
Chapter 8 Direct Memory Access Controller (DMAC) This chapter describes DMAC present in the ARM926EJ-S Development Chip. It contains the following section: • About the Direct Memory Access Controller (PL080) on page 8-2 • Functional description on page 8-4 • DMA signals on pads on page 8-7. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
Direct Memory Access Controller (DMAC) 8.1 About the Direct Memory Access Controller (PL080) The DMAC is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral that is developed, tested, and licensed by ARM Limited. The DMAC is an AMBA AHB module, and has two masters and one slave that connect to the AHB bus matrix. The release version used is PL080 DMAC REL1v1. The base address for the DMAC registers is 0x10130000.
Direct Memory Access Controller (DMAC) • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the peripheral. • Internal four-word FIFO per channel. • Supports 8, 16, and 32-bit wide transactions. • Big-endian and little-endian support. The PrimeCell DMAC defaults to little-endian mode on reset. • Separate and combined DMA error and DMA count interrupt requests.
Direct Memory Access Controller (DMAC) 8.2 Functional description The block diagram for the DMA controller interface is shown in Figure 8-1. ARM926EJ-S Dev.
Direct Memory Access Controller (DMAC) 8.2.1 Peripheral integration The allocation of the DMAC peripheral request lines is defined in Table 8-1. Table 8-1 DMA channel allocation DMA requester DMA channel UART0 Tx 15 UART0 Rx 14 UART1 Tx 13 UART1 Rx 12 UART2 Tx 11 UART2 Rx 10 SSP Tx 9 SSP Rx 8 SCI Tx 7 SCI Rx 6 External DMA request [5:0] 5:0 The master interfaces of the DMAC both drive single master AHBs.
Direct Memory Access Controller (DMAC) 8.2.2 Registers The PrimeCell DMAC enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream is configured to provide unidirectional DMA transfers for a single source and destination. For example, a bidirectional serial port requires one stream for transmit and one for receive.
Direct Memory Access Controller (DMAC) 8.3 DMA signals on pads The pad input and output signals for the DMAC are shown in Table 8-1. These signals are for connection to external DMA capable peripherals. Table 8-1 DMA request and response signal descriptions ARM DDI 0287B Name Type Description DMACBREQ[5:0] Input DMA burst transfer request. DMACSREQ[5:0] Input DMA single transfer request. DMACLBREQ[5:0] Input DMA last burst transfer request.
Direct Memory Access Controller (DMAC) 8-8 Copyright © 2004, 2006 ARM Limited. All rights reserved.
Chapter 9 General Purpose Input Output (GPIO) This chapter describes the GPIOs in the ARM926EJ-S Development Chip. It contains the following sections: • About the ARM PrimeCell GPIO (PL061) on page 9-2 • Functional description on page 9-3 • GPIO signals on pads on page 9-5. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
General Purpose Input Output (GPIO) 9.1 About the ARM PrimeCell GPIO (PL061) The PrimeCell GPIO is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral that is developed, tested, and licensed by ARM. The four GPIOs connect to the core APB. The release version used is PL061 GPIO 1v0. The base address for the GPIO registers are 0x101E4000, 0x101E5000, 0x101E6000, and 0x101E7000.
General Purpose Input Output (GPIO) 9.2 Functional description Figure 9-1 shows the PrimeCell GPIO control circuit and external interfaces for one of the four GPIO interfaces.
General Purpose Input Output (GPIO) Note For GPIO3, the GPAFIN[6:0] signals are not used, but the GPAFIN[7] signal is connected to the system controller BATOK signal. For GPIO0, GPIO1, and GPIO2, none of the GPAFIN[7:0] signals are not used 9.2.1 Registers The base address of the PrimeCell GPIO’s are: GPIO0 0x101E4000 GPIO1 0x101E5000 GPIO2 0x101E6000 GPIO2 0x101E7000.
General Purpose Input Output (GPIO) 9.3 GPIO signals on pads Table 9-2 describes the signals from the PrimeCell GPIO to input/output pads of the chip. Table 9-2 Pad signal descriptions ARM DDI 0287B Name Description GPx_[7:0] These I/O signals are the output from the GPIO0, GPIO1, GPIO2, and GPIO3. The GPIOEN[7:0] signals in the PL061 control the data direction. Copyright © 2004, 2006 ARM Limited. All rights reserved.
General Purpose Input Output (GPIO) 9-6 Copyright © 2004, 2006 ARM Limited. All rights reserved.
Chapter 10 Multi-Port Memory Controller (MPMC) This chapter describes the MPMC in the ARM926EJ-S Development Chip. It contains the following sections: • About the ARM PrimeCell MPMC (GX175) on page 10-2 • Functional description on page 10-6 • MPMC signals on pads on page 10-8. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
Multi-Port Memory Controller (MPMC) 10.1 About the ARM PrimeCell MPMC (GX175) The PrimeCell MPMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral that is developed, tested, and licensed by ARM Limited. It connects to the AHB bus matrix. The release version used for the controller is GX175 MPMC r0p0-00alp2. The base address for the MPMC control registers is 0x10110000.
Multi-Port Memory Controller (MPMC) • Power-saving modes dynamically control MPMCCKEOUT and MPMCCLKOUT. • Dynamic memory self-refresh mode supported by a Power Management Unit (PMU) interface or by software. • Controller supports 2K, 4K, and 8K row address synchronous memory parts. That is, typical 512Mb, 256Mb, 128Mb, and 16Mb parts, with 8, 16, or 32 DQ (data) bits per device. • Two reset domains enable dynamic memory contents to be preserved over a soft reset.
Multi-Port Memory Controller (MPMC) 10.1.2 Supported dynamic memory devices This section provides examples of dynamic memory devices that are supported by the PrimeCell MPMC. Note This is not an exhaustive list of supported devices. The following JEDEC SDRAM devices are supported: • 16Mb devices: — Micron MT48LC1M16A1S — Samsung K4S160822D-G/F — Samsung K4S641632C. • 64Mb devices: — Micron MT48LC2M32B2-6 — Micron MT28S4M162C-10 — Elpida VDP4564323-10 — Hitachi HM5264805F-75.
Multi-Port Memory Controller (MPMC) 10.1.3 Supported static memory devices This section provides examples of static memory devices that are supported by the PrimeCell MPMC. Note This is not an exhaustive list of supported devices. Static devices on the MPMC cannot be used as boot memory.
Multi-Port Memory Controller (MPMC) 10.2 Functional description Figure 10-1 shows a block diagram of the PrimeCell MPMC. For details on the static memory multiplexor, see Functional description on page 13-5. ARM926EJ-S Dev.
Multi-Port Memory Controller (MPMC) 10.2.1 Implementation details The following outputs are unconnected: • MPMCDLLCALIBREQ • MPMCDQSOUT[1:0] • nMPMCCLKOUT[3:0] • nMPMCDQSOUTEN[3:0] • MPMCEBIREQ. Note Booting from memory controlled by the MPMC is not supported. Configuration signals relating to configuring the reset state of the MPMC are not used. You must configure the MPMC before you use it to control memory on either the dynamic or static memory buses.
Multi-Port Memory Controller (MPMC) 10.3 MPMC signals on pads The pad interface and control signals are described in Table 10-1. Table 10-1 Pad interface and control signal descriptions Name Type MPMCADDROUT[25:15] Output Source/ destination MPMC/SSMC multiplexor Description Address output. Used for static memory devices. Note SDRAM memories only use MPMCADDROUT[14:0]. Static memories use bits MPMCADDROUT[25:0]. MPMCADDROUT[14:0] Output Pad and MPMC/SSMC multiplexor Address output.
Multi-Port Memory Controller (MPMC) Table 10-1 Pad interface and control signal descriptions (continued) Name Type Source/ destination Description nMPMCRASOUT Output Pad Row address strobe. Used for SDRAM devices. nMPMCRPOUT Output Pad Reset power down to SyncFlash memory. Used for the dynamic memory controller. nMPMCSTCSOUT[3:0] Output MPMC/SSMC multiplexor Static memory chip selects. Default active LOW. Used for static memory devices.
Multi-Port Memory Controller (MPMC) 10-10 Copyright © 2004, 2006 ARM Limited. All rights reserved.
Chapter 11 Real-Time Clock (RTC) This chapter describes the Real Time Clock (RTC) PrimeCell in the ARM926EJ-S Development Chip. It contains the following sections: • About the Real Time Clock on page 11-2 • Functional description on page 11-3. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
Real-Time Clock (RTC) 11.1 About the Real Time Clock The PrimeCell Real Time Clock (RTC) PL031 is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-a-Chip (SoC) peripheral that is developed, tested, and licensed by ARM. The RTC connects to the core APB. The RTC comprises: • an AMBA APB interface • a 32-bit counter • a 32-bit match register • a 32-bit comparator. The CPU reads and writes data, and control and status information through the AMBA APB interface.
Real-Time Clock (RTC) 11.2 Functional description The release version used is PL031 RTC 1v0. The base address for the RTC control registers is 0x101E8000. For more information on the controller, see the ARM PrimeCell Timer Module (SP804) Technical Reference Manual. The PrimeCell RTC can be used to provide a basic alarm function or long time base counter. This is achieved by generating an interrupt signal after counting for a programmed number of cycles of a real-time clock input.
Real-Time Clock (RTC) 11.2.1 Registers The base address of the PrimeCell RTC is 0x101E8000. The following locations are reserved, and must not be used during normal operation: 11.2.2 • locations at offsets 0x20–0x7C and 0x94–0xFCC are reserved for possible future extensions • locations at offsets 0x80–0x90 are reserved for test purposes • locations at offsets 0xFD0–0xFDC are reserved for future identification registers.
Chapter 12 Smart Card Interface (SCI) This chapter describes the SCI in the ARM926EJ-S Development Chip. It contains the following sections: • About the ARM SCI on page 12-2 • Functional description on page 12-4 • SCI signals on pads on page 12-6. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
Smart Card Interface (SCI) 12.1 About the ARM SCI The PrimeCell Smart Card Interface (SCI) PL131 is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-a-Chip (SoC) peripheral that is developed, tested, and licensed by ARM. The SCI connects to the DMA APB. The release version used is PL131 SCI 1v0. The base address for the SCI control registers is 0x101F0000. For more detailed information on the controller, see the ARM PrimeCell Smart Card Interface Technical Reference Manual.
Smart Card Interface (SCI) 12.1.
Smart Card Interface (SCI) 12.2 Functional description The block diagram of the SCI is shown in Figure 12-1. ARM926EJ-S Dev.
Smart Card Interface (SCI) 12.2.3 Interrupts There are fifteen interrupts generated within the PrimeCell SCI. The interrupt mask set or clear register, SCIIMSC, provides a way of masking each of these individual interrupts. Setting the appropriate mask bit HIGH enables the interrupt, all of these are active HIGH. Individual interrupts are shown in Table 12-1.
Smart Card Interface (SCI) 12.3 SCI signals on pads The SCI interface signals connected to the input/output pads are listed in Table 12-2. Table 12-2 SCI signals 12-6 Name Type Description SCICLKIN Input PrimeCell SCI clock input. SCIDATAIN Input PrimeCell SCI serial data input. nSCICLKOUTEN Output Tristate output buffer control (active LOW). SCICLKOUT Output Clock output. nSCIDATAOUTEN Output Data output enable (typically drives an open-drain configuration, active LOW).
Chapter 13 Synchronous Static Memory Controller (SSMC) This chapter describes the SSMC in the ARM926EJ-S Development Chip. It contains the following sections: • About the ARM PrimeCell SSMC (PL093) on page 13-2 • Functional description on page 13-5 • SSMC signals on pads on page 13-9. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
Synchronous Static Memory Controller (SSMC) 13.1 About the ARM PrimeCell SSMC (PL093) The PrimeCell Synchronous Static Memory Controller (SSMC) is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip peripheral that is developed, tested, and licensed by ARM. The SSMC connects to the AHB bus matrix. The release version used is PL093 SSMC r0p0-00ltd0. The base address for the SSMC control registers is 0x10100000.
Synchronous Static Memory Controller (SSMC) 13.1.2 • external asynchronous wait control • configurable size at reset for boot memory bank using external control pins • system testing using externally applied TIC vectors through built-in TIC AMBA master block • support to interface to another memory controller using an External Bus Interface (EBI) • multiple memory clock frequencies available, HCLK, HCLK/2, and HCLK/3 • eight word, 32-bit, wrapping reads from 16-bit or 32-bit memory.
Synchronous Static Memory Controller (SSMC) 13.1.3 Supported memory devices The PrimeCell SSMC can be connected to synchronous and asynchronous memory devices.
Synchronous Static Memory Controller (SSMC) 13.2 Functional description The SSMC core performs read and write accesses to external memory through the AMBA AHB slave interface. Figure 13-1 shows a block diagram of the SSMC core. Figure 13-2 on page 13-6 and Figure 13-3 on page 13-7 shows the data and control signal multiplexing.
Synchronous Static Memory Controller (SSMC) If the select signal CFGMPMCnSMC is HIGH, the MPMC controller is used in place of the SSMC. The multiplexing circuitry for the static address, data, and control signals is shown in Figure 13-2 and Figure 13-3 on page 13-7. nMPMCWE ARM926EJ-S Dev.
Synchronous Static Memory Controller (SSMC) ARM926EJ-S Dev. Chip Byte output enables nMPMCDATAOUTEN[3:0] MPMCDATA[31:0] MPMCDATAOUT[31:0] Mux MPMCDATAIN[31:0] Mux GX175 MPMC Byte output enables nMPMCOEOUT CFGMPMCnSMC PL093 SSMC SMDATAOUT[31:0] Mux nSMDATAEN[3:0] SMDATA[31:0] SMDATAIN[31:0] Figure 13-3 Data multiplexor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
Synchronous Static Memory Controller (SSMC) 13.2.1 Implementation details Table 13-1 describes the internal signals that are configurable or tied off. Table 13-1 Internal signal descriptions Source/ destination Signal name Type SMBIGENDIAN Input Configuration control This static configuration bit indicates the type of endianness of the memory system: 0 = little-endian 1 = big-endian. SMBUSBACKOFFEBI Input LOW Release bus signal, tells SSMC to release bus. Only used when EXTBUSMUX is tied to one.
Synchronous Static Memory Controller (SSMC) 13.3 SSMC signals on pads Table 13-2 describes the signals to the input/output pads. Table 13-2 Pad signals Signal name Direction Description nSMBURSTWAIT[0] Input Synchronous burst wait input used by the external device to delay a synchronous burst transfer. SMBLS7POL Input This is used to define the reset value of bit 6 in SMBCR7 (nSMBLS): 0 = nSMBLS is active low (default) 1 = nSMBLS is active high.
Synchronous Static Memory Controller (SSMC) Table 13-2 Pad signals (continued) Signal name Direction Description nSMCS6 Output Chip select for bank 6 of external memory, default active LOW. nSMCS7 Output Chip select for bank 7 of external memory, default active LOW. nSMDATAEN[3:0] Output Tristate input/output pad enable for the byte lanes of the external memory data bus SMDATA[31:0], active LOW. Enables the byte lanes [31:24], [23:16], [15:8], and [7:0] of the data bus independently.
Chapter 14 Synchronous Serial Port (SSP) This chapter describes the SSP in the ARM926EJ-S Development Chip. It contains the following sections: • About the ARM PrimeCell SSP (PL022) on page 14-2 • Functional description on page 14-4 • SSP signals on pads on page 14-6. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
Synchronous Serial Port (SSP) 14.1 About the ARM PrimeCell SSP (PL022) The PrimeCell Synchronous Serial Port (SSP) is an Advanced Microcontroller Bus Architecture (AMBA) slave block that connects to the DMA APB. The PrimeCell SSP is an AMBA compliant System-on-Chip (SoC) peripheral that is developed, tested, and licensed by ARM. The release version used is PL022 SSP REL1v2. The base address for the SSP control registers is 0x101F4000.
Synchronous Serial Port (SSP) • Programmable choice of interface operation, SPI, Microwire, or TI synchronous serial. • Programmable data frame size from 4 to 16 bits. • Independent masking of transmit FIFO, receive FIFO, and receive overrun interrupts. • Internal loopback test mode available. • Support for Direct Memory Access (DMA). • Identification registers that uniquely identify the PrimeCell SSP. These can be used by an operating system to automatically configure itself.
Synchronous Serial Port (SSP) 14.2 Functional description This section describes the function of the SSP controller. For detailed information on the internal organization and the SSP registers, see the ARM PrimeCell Synchronous Serial Port Controller (PL022) Technical Reference Manual. 14.2.1 Using an external reference clock In the slave mode of operation, the SSPCLKIN signal from the external master is double synchronized and then delayed to detect an edge.
Synchronous Serial Port (SSP) 14.2.2 Registers The base address of the PrimeCell SSP is 0x101F4000. The following locations are reserved, and must not be used during normal operation: 14.2.3 • locations at offsets 0x028–0x07C and 0xFD0–0xFDC are reserved for possible future extensions • locations at offsets 0x080–0x088 are reserved for test purposes. Interrupts There are five interrupts generated by the PrimeCell SSP.
Synchronous Serial Port (SSP) 14.3 SSP signals on pads The signals connected to pads are listed in Table 14-1. Table 14-1 Pad signal descriptions 14-6 Name Type Description SSPFSSOUT Output PrimeCell SSP frame, or slave select output (master). SSPCLKOUT Output PrimeCell SSP clock output (master). SSPRXD Input PrimeCell SSP receive data input. SSPTXD Output PrimeCell SSP transmit data output. nSSPCTLOE Output Output enable signal (active LOW) for SSPCLKOUT output from the PrimeCell SSP.
Chapter 15 Dual Timer/Counters This chapter describes the SP804 timer/counters in the ARM926EJ-S Development Chip. It contains the following section: • About the ARM Dual-Timer module (SP804) on page 15-2 • Functional description on page 15-3. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
Dual Timer/Counters 15.1 About the ARM Dual-Timer module (SP804) The ARM Dual-Timer module is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral developed, tested, and licensed by ARM Limited. For more information, see the AMBA Specification (Rev 2.0). The release state of the ARM Dual-Timer module used in the ARM926EJ-S Development Chip is SP804-r1p0. The base address for the Dual-Timer control registers are 0x101E2000 and 0x101E3000.
Dual Timer/Counters 15.2 Functional description This section gives a basic overview of the Dual-Timer module operation. The Dual-Timer module consists of two identical programmable Free Running Counters (FRCs) that can be configured for 32-bit or 16-bit operation and one of three timer modes; • free-running • periodic • one-shot. The FRCs operate from a common timer clock, a buffered version of HCLK with each FRC having its own clock enable input, TIMCLKEN1 and TIMCLKEN2.
Dual Timer/Counters Figure 15-1 shows a simplified block diagram of the module. At reset, the timers are clocked by an external reference on the REFCLK32K input. You can use the system controller to change the timer reference to the TIMCLKEXT input signal (see Clock control on page 2-13). HCLK Clock control logic Core APB AMBA APB Interface Note In Figure 15-1, test logic is not shown for clarity.
Dual Timer/Counters 15.2.2 Programmable parameters The following Dual-Timer module parameters are programmable: • free-running, periodic, or one-shot timer modes • 32-bit or 16-bit timer operation • prescaler divider of 1, 16, or 256 • interrupt generation enable and disable • interrupt masking. 15.2.3 Registers The base address of the PrimeCell timers are: Timer01 0x101E2000. Timer23 0x101E3000. Some locations within the memory range are reserved: • offsets 0x40–0xEFC • offsets 0xF08–0xFDC.
Dual Timer/Counters 15-6 Copyright © 2004, 2006 ARM Limited. All rights reserved.
Chapter 16 UART Controller This chapter describes the UART peripherals in the ARM926EJ-S Development Chip. It contains the following sections: • About the ARM PrimeCell UART (PL011) on page 16-2 • Functional description on page 16-4 • UART signals on pads on page 16-8. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
UART Controller 16.1 About the ARM PrimeCell UART (PL011) The PrimeCell UART is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral that is developed, tested, and licensed by ARM. The release version used is PL011 UART 1v3. The base address for the UART control registers are 0x101F1000, 0x101F2000, and 0x101F3000. For more information on the controller, see the ARM PrimeCell UART (PL011) Technical Reference Manual.
UART Controller • Independent masking of transmit FIFO, receive FIFO, receive timeout, modem status, and error condition interrupts. Note The interrupts signals from each UART are combined into a single interrupt that is output to the VIC. • Support for Direct Memory Access (DMA). • False start bit detection. • Line break generation and detection. • Support of the modem control functions CTS, DCD, DSR, RTS, DTR, and RI. • Programmable hardware flow control.
UART Controller 16.2 Functional description Figure 16-1 shows a block diagram of the PrimeCell UARTs and the interface connections. Note Not all of the UART1 and UART2 signals are connected to the pads. Other than the tied-off signals, the operation of UART1 and UART2 is the same as UART0. Figure 16-1 PrimeCell UART block diagram 16-4 Copyright © 2004, 2006 ARM Limited. All rights reserved.
UART Controller 16.2.1 Clock signals The UARTs can be clocks from an internal reference or the external reference clock UARTCLKEXT can be selected. The frequency selected for UARTCLK must accommodate the required range of baud rates: FUARTCLK (min) >= 16 x baud_rate (max) FUARTCLK(max) <= 16 x 65535 x baud_rate (min) For example, for a range of baud rates from 110–460800 baud the UARTCLK frequency must be within the range 7.3728–115MHz.
UART Controller Programmable parameters The following key parameters are programmable: • communication baud rate, integer, and fractional parts • number of data bits • number of stop bits • parity mode • FIFO enable (16 deep) or disable (1 deep) • FIFO trigger levels selectable between 1/8, 1/4, 1/2, 3/4, and 7/8. • internal nominal 1.8432MHz clock frequency (1.42–2.12MHz) to generate low-power mode shorter bit duration • hardware flow control.
UART Controller 16.2.5 Implementation details The following inputs are tied off: • nUART1DCD is tied HIGH • nUART1DSR is tied HIGH • nUART1RI is tied HIGH • SIRIN1 is tied LOW • nUART2DCD is tied HIGH • nUART2DSR is tied HIGH • nUART2RI is tied HIGH • SIRIN2 is tied LOW. The following outputs are unconnected: • nUART1DTR • nUART1Out1 • nUART1Out2 • nSIROUT1 • nUART2DTR • nUART2Out1 • nUART2Out2 • nSIROUT2.
UART Controller 16.3 UART signals on pads The signals connected to pads are listed in Table 16-1. Table 16-1 Pad signal descriptions 16-8 Name Direction Description nUART0CTS nUART1CTS nUART2CTS Input UART Clear To Send modem status signal, active LOW. The condition of this signal can be read from the UARTFR register. nUART0DCD Input UART Data Carrier Detect modem status signal, active LOW. The condition of this signal can be read from the UARTFR register.
UART Controller Table 16-1 Pad signal descriptions (continued) ARM DDI 0287B Name Direction Description nUART0DTR Output UART Data Terminal Ready modem status signal, active LOW. The reset value is 0. (nUARTDTR is not used on UART1 and UART2.) nUART0Out1 nUART0Out2 Output UART modem status signal, active LOW. The reset value is 0. (nUARTOut1 is not used on UART1 and UART2.) UART0TXD UART1TXD UART2TXD Output UART Transmit Serial Data. Defaults to the marking state 1, when reset.
UART Controller 16-10 Copyright © 2004, 2006 ARM Limited. All rights reserved.
Chapter 17 Vectored Interrupt Controller (VIC) This chapter describes the vectored-interrupt controller in the ARM926EJ-S Development Chip. It contains the following sections: • About the ARM PrimeCell Vectored Interrupt Controller (PL190) on page 17-2 • Functional description on page 17-4 • VIC signals on pads on page 17-11. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
Vectored Interrupt Controller (VIC) 17.1 About the ARM PrimeCell Vectored Interrupt Controller (PL190) The PrimeCell Vectored Interrupt Controller (VIC) is an Advanced Microcontroller Bus Architecture (AMBA) compliant, System-on-Chip (SoC) peripheral that is developed, tested, and licensed by ARM. The release version used is PL190 VIC 1v1. The base address for the VIC control registers is 0x10140000.
Vectored Interrupt Controller (VIC) Only a single FIQ source at a time is generally used in a system, to provide a true low-latency interrupt. This has the following benefits: • You can execute the interrupt service routine directly without determining the source of the interrupt. • Interrupt latency is reduced. You can use the banked registers available for FIQ interrupts more efficiently, because a context save is not required. There are 32 interrupt lines.
Vectored Interrupt Controller (VIC) 17.2 Functional description Figure 17-1 shows a block diagram of the PrimeCell VIC interface. ARM926EJ-S Dev.
Vectored Interrupt Controller (VIC) 17.2.1 Interrupt request logic The interrupt request logic receives the interrupt requests from the peripheral and combines them with the software interrupt requests. It then masks out the interrupt requests that are not enabled, and routes the enabled interrupt requests to either IRQ or FIQ. Figure 17-2 shows a block diagram of the interrupt request logic. Figure 17-2 Interrupt request logic ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
Vectored Interrupt Controller (VIC) 17.2.2 Nonvectored FIQ interrupt logic The nonvectored FIQ interrupt logic generates the FIQ interrupt signal by combining the FIQ interrupt requests in the interrupt controller and any requests from daisy-chained interrupt controllers. Figure 17-3 shows a block diagram of the nonvectored FIQ interrupt logic. Figure 17-3 Nonvectored FIQ interrupt logic 17.2.
Vectored Interrupt Controller (VIC) 17.2.4 Vectored interrupt block There are 16 vectored interrupt blocks. The vectored interrupt blocks receive the IRQ interrupt requests and set VectIRQx if the following are true: • the selected interrupt is active • the selected interrupt is the currently highest requesting interrupt. Each vectored interrupt block also provides a VectorAddrx[31:0] output for use in the interrupt priority block. Figure 17-5 shows a block diagram of two of the vectored interrupt blocks.
Vectored Interrupt Controller (VIC) 17.2.5 Interrupt priority logic The interrupt priority block prioritizes the following requests: • nonvectored interrupt requests • vectored interrupt requests • external interrupt requests. The highest-priority request generates an IRQ interrupt if the interrupt is not currently being serviced. Figure 17-6 shows a block diagram of the interrupt priority logic. Note nVICIRQIN is the daisy-chained IRQ request input.
Vectored Interrupt Controller (VIC) 17.2.6 Vectored interrupts A vectored interrupt is only generated if the following are true: • it is enabled in the interrupt enable register, VICIntEnable • it is set to generate an IRQ interrupt in the interrupt select register, VICIntSelect • it is enabled in the relevant vector control register, VICVectCntl0-VICVectCntl15]. This prevents multiple interrupts being generated from a single interrupt request if the controller is incorrectly programmed. 17.2.
Vectored Interrupt Controller (VIC) 17.2.9 Implementation details The tied off or unused signals are shown in Table 17-1. Table 17-1 Tied off or unused signals 17-10 Name Source/ destination VICVECTADDRIN [31:0] LOW Connects to the VICVECTADDROUT[31:0] signal of the previous VIC if daisy chaining is used. Connects to LOW if the VIC is not daisy-chained. VICVECTADDROUT [31:0] Not used Connects to the VICVECTADDRIN[31:0] signal of the next VIC if daisy chaining is used.
Vectored Interrupt Controller (VIC) 17.3 VIC signals on pads The interrupt request signals connected to pads are listed in Table 17-2. Table 17-2 Interrupt controller pad signals PrimeCell name Dev.
Vectored Interrupt Controller (VIC) 17-12 Copyright © 2004, 2006 ARM Limited. All rights reserved.
Chapter 18 ARM Vector Floating Point Coprocessor (VFP9) This chapter describes the VFP9 coprocessor present in the ARM926EJ-S Development Chip. It contains the following sections: • About the VFP9-S coprocessor on page 18-2 • VFP9-S system control and status registers on page 18-4. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
ARM Vector Floating Point Coprocessor (VFP9) 18.1 About the VFP9-S coprocessor The VFP9-S coprocessor is an implementation of the Vector Floating-point Architecture version 2 (VFPv2). The release version used is VFP9-S r1p1. The coprocessor provides low-cost floating-point computation that is fully compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, referred to in this document as the IEEE 754 standard.
ARM Vector Floating Point Coprocessor (VFP9) 18.2 ARMv5TE coprocessor extensions There are four coprocessor extensions used with the VFP9: ARM DDI 0287B FMDRR The FMDRR instruction transfers data from two ARM registers to a VFP9-S double-precision register. The ARM registers do not have to be contiguous. FMRRD The FMRRD instruction transfers data in a VFP9-S double-precision register to two ARM registers. The ARM registers do not have to be contiguous.
ARM Vector Floating Point Coprocessor (VFP9) 18.3 VFP9-S system control and status registers The VFP9-S coprocessor provides sufficient information for processing all exception conditions encountered by the hardware.
ARM Vector Floating Point Coprocessor (VFP9) Access to the FPEXC, FPINST, and FPINST2 registers is possible only in a privileged mode, and does not trigger exceptions. Use the FMRX instruction to store these registers and the FMXR instruction to load them. Table 18-1 describes access to these registers.
ARM Vector Floating Point Coprocessor (VFP9) 18.4 Modes of operation The VFP9-S coprocessor provides full IEEE 754 standard compatibility through a combination of hardware and software. There are rare cases that require significant additional compute time to resolve correctly according to the requirements of the IEEE 754 standard. For instance, the VFP9-S coprocessor does not process subnormal input values directly.
ARM Vector Floating Point Coprocessor (VFP9) • A float-to-integer conversion that has the potential to create an integer that cannot be represented in the destination integer format when Invalid Operation exceptions are enabled.
ARM Vector Floating Point Coprocessor (VFP9) 18.4.4 RunFast Mode RunFast mode is the combination of the following conditions: • the VFP9-S coprocessor is in Flush-to-Zero mode • the VFP9-S coprocessor is in Default NaN mode • all exception enable bits are cleared.
Chapter 19 Watchdog Timer This chapter describes the Watchdog timer in the ARM926EJ-S Development Chip. It contains the following sections: • About the Watchdog module (SP805) on page 19-2 • Functional description on page 19-3. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
Watchdog Timer 19.1 About the Watchdog module (SP805) The Watchdog module is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral developed, tested, and licensed by ARM Limited. The release state of the Watchdog Module used in the ARM926EJ-S Development Chip is SP805-r1p0. The base address for the Watchdog control registers is 0x101E1000. For more information on the controller, see the ARM PrimeCell Watchdog Controller (SP805) Technical Reference Manual.
Watchdog Timer 19.2 Functional description Figure 19-1 shows a simplified block diagram of the Watchdog module.
Watchdog Timer disables write accesses to all registers except the Lock Register. This feature protects the Watchdog module registers from being spuriously changed by runaway software that might otherwise disable the Watchdog module operation. 19.2.1 Programmable parameters The following Watchdog module parameters are programmable: • interrupt generation enable/disable • interrupt masking • reset signal generation enable and/disable • interrupt interval. 19.2.
Appendix A Signals on Pads This appendix lists the signals on the ARM926EJ-S Development Chip pads. It contains the following section: • Pad signals by function on page A-2. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
Signals on Pads A.1 Pad signals by function Table A-1 lists the pad signals and the signal characteristics: • The Function column identifies the major functional block. • The Type column indicates the signal direction: I Input IPU Input with internal pull-up O Output B Bidirectional I/O T Tristate output PIO Power to I/O PC Power to core. • The Drive column indicates the drive strength in mA. • The BGA column is the pad identifier. Note BGA pads not listed are ground.
Signals on Pads Table A-1 Pad signals (continued) Function Signal Description Type Drive BGA AHB M1 HADDRM1[9] Address bus T 8 AJ33 AHB M1 HADDRM1[10] Address bus T 8 AF30 AHB M1 HADDRM1[11] Address bus T 8 AH31 AHB M1 HADDRM1[12] Address bus T 8 AE30 AHB M1 HADDRM1[13] Address bus T 8 AH32 AHB M1 HADDRM1[14] Address bus T 8 AF29 AHB M1 HADDRM1[15] Address bus T 8 AH33 AHB M1 HADDRM1[16] Address bus T 8 AH34 AHB M1 HADDRM1[17] Address bus T 8 AG31
Signals on Pads Table A-1 Pad signals (continued) A-4 Function Signal Description Type Drive BGA AHB M1 HBURSTM1[2] Transfer burst length T 8 AD34 AHB M1 HBUSREQM1 Master bus request O 8 AL32 AHB M1 HDATAM1[0] Data bus B 8 AB32 AHB M1 HDATAM1[1] Data bus B 8 AB33 AHB M1 HDATAM1[2] Data bus B 8 AB34 AHB M1 HDATAM1[3] Data bus B 8 Y28 AHB M1 HDATAM1[4] Data bus B 8 AA31 AHB M1 HDATAM1[5] Data bus B 8 Y29 AHB M1 HDATAM1[6] Data bus B 8 AA32 AHB M1
Signals on Pads Table A-1 Pad signals (continued) Function Signal Description Type Drive BGA AHB M1 HDATAM1[23] Data bus B 8 V28 AHB M1 HDATAM1[24] Data bus B 8 U33 AHB M1 HDATAM1[25] Data bus B 8 V30 AHB M1 HDATAM1[26] Data bus B 8 U32 AHB M1 HDATAM1[27] Data bus B 8 U28 AHB M1 HDATAM1[28] Data bus B 8 U31 AHB M1 HDATAM1[29] Data bus B 8 T34 AHB M1 HDATAM1[30] Data bus B 8 T33 AHB M1 HDATAM1[31] Data bus B 8 U29 AHB M1 HGRANTM1 Arbiter bus gran
Signals on Pads Table A-1 Pad signals (continued) A-6 Function Signal Description Type Drive BGA AHB M2 HADDRM2[2] Address bus T 8 M33 AHB M2 HADDRM2[3] Address bus T 8 R28 AHB M2 HADDRM2[4] Address bus T 8 M32 AHB M2 HADDRM2[5] Address bus T 8 P30 AHB M2 HADDRM2[6] Address bus T 8 M31 AHB M2 HADDRM2[7] Address bus T 8 P29 AHB M2 HADDRM2[8] Address bus T 8 L34 AHB M2 HADDRM2[9] Address bus T 8 L33 AHB M2 HADDRM2[10] Address bus T 8 L32 AHB M2 H
Signals on Pads Table A-1 Pad signals (continued) Function Signal Description Type Drive BGA AHB M2 HADDRM2[27] Address bus T 8 M29 AHB M2 HADDRM2[28] Address bus T 8 H31 AHB M2 HADDRM2[29] Address bus T 8 L30 AHB M2 HADDRM2[30] Address bus T 8 G34 AHB M2 HADDRM2[31] Address bus T 8 L28 AHB M2 HBURSTM2[0] Transfer burst length T 8 L29 AHB M2 HBURSTM2[1] Transfer burst length T 8 F33 AHB M2 HBURSTM2[2] Transfer burst length T 8 K29 AHB M2 HBUSREQM2 Mas
Signals on Pads Table A-1 Pad signals (continued) A-8 Function Signal Description Type Drive BGA AHB M2 HDATAM2[16] Data bus B 8 C30 AHB M2 HDATAM2[17] Data bus B 8 E27 AHB M2 HDATAM2[18] Data bus B 8 B30 AHB M2 HDATAM2[19] Data bus B 8 A30 AHB M2 HDATAM2[20] Data bus B 8 E29 AHB M2 HDATAM2[21] Data bus B 8 F26 AHB M2 HDATAM2[22] Data bus B 8 D29 AHB M2 HDATAM2[23] Data bus B 8 E26 AHB M2 HDATAM2[24] Data bus B 8 C29 AHB M2 HDATAM2[25] Data bu
Signals on Pads Table A-1 Pad signals (continued) Function Signal Description Type Drive BGA AHB M2 HSIZEM2[0] Transfer size T 8 K30 AHB M2 HSIZEM2[1] Transfer size T 8 F34 AHB M2 HTRANSM2[0] Transfer type T 8 G32 AHB M2 HTRANSM2[1] Transfer type T 8 G31 AHB M2 HWRITEM2 Write transfer T 8 G33 AHB S HADDRS[0] Address bus I - D7 AHB S HADDRS[1] Address bus I - F10 AHB S HADDRS[2] Address bus I - A6 AHB S HADDRS[3] Address bus I - G10 AHB S HADDRS[4
Signals on Pads Table A-1 Pad signals (continued) A-10 Function Signal Description Type Drive BGA AHB S HADDRS[20] Address bus I - F5 AHB S HADDRS[21] Address bus I - K7 AHB S HADDRS[22] Address bus I - F4 AHB S HADDRS[23] Address bus I - K6 AHB S HADDRS[24] Address bus I - F3 AHB S HADDRS[25] Address bus I - K5 AHB S HADDRS[26] Address bus I - F1 AHB S HADDRS[27] Address bus I - L7 AHB S HADDRS[28] Address bus I - G5 AHB S HADDRS[29] Address
Signals on Pads Table A-1 Pad signals (continued) Function Signal Description Type Drive BGA AHB S HDATAS[10] Data bus B 8 B11 AHB S HDATAS[11] Data bus B 8 G14 AHB S HDATAS[12] Data bus B 8 C11 AHB S HDATAS[13] Data bus B 8 F13 AHB S HDATAS[14] Data bus B 8 D11 AHB S HDATAS[15] Data bus B 8 A10 AHB S HDATAS[16] Data bus B 8 B10 AHB S HDATAS[17] Data bus B 8 G13 AHB S HDATAS[18] Data bus B 8 C10 AHB S HDATAS[19] Data bus B 8 G12 AHB S HDATA
Signals on Pads Table A-1 Pad signals (continued) A-12 Function Signal Description Type Drive BGA AHB S HPROTS[2] Protection Control I - H1 AHB S HPROTS[3] Protection Control I - N6 AHB S HREADYS Transfer finished B 8 E10 AHB S HRESPS[0] Transfer response T 8 B7 AHB S HRESPS[1] Transfer response T 8 C7 AHB S HSELS Slave select I - N5 AHB S HSIZES[0] Transfer size I - L5 AHB S HSIZES[1] Transfer size I - H4 AHB S HTRANSS[0] Transfer type I - M7 A
Signals on Pads Table A-1 Pad signals (continued) Function Signal Description Type Drive BGA AHB Monitor AHBMONITOR[14] Debug information O 8 F23 AHB Monitor AHBMONITOR[15] Debug information O 8 A26 AHB Monitor AHBMONITOR[16] Debug information O 8 C25 AHB Monitor AHBMONITOR[17] Debug information O 8 B25 AHB Monitor AHBMONITOR[18] Debug information O 8 G22 AHB Monitor AHBMONITOR[19] Debug information O 8 A25 AHB Monitor AHBMONITOR[20] Debug information O 8 F22
Signals on Pads Table A-1 Pad signals (continued) A-14 Function Signal Description Type Drive BGA CLCDC CLD[2] Data bus O 4 AL23 CLCDC CLD[3] Data bus O 4 AP24 CLCDC CLD[4] Data bus O 4 AK21 CLCDC CLD[5] Data bus O 4 AN24 CLCDC CLD[6] Data bus O 4 AK22 CLCDC CLD[7] Data bus O 4 AL24 CLCDC CLD[8] Data bus O 4 AJ21 CLCDC CLD[9] Data bus O 4 AP25 CLCDC CLD[10] Data bus O 4 AH21 CLCDC CLD[11] Data bus O 4 AN25 CLCDC CLD[12] Data bus O 4 A
Signals on Pads Table A-1 Pad signals (continued) Function Signal Description Type Drive BGA CLCDC CLPOWER Panel power enable O 4 AM22 Clock HCLKM1 Asynchronous AHB Clock In I - T32 Clock HCLKM2 Asynchronous AHB Clock In I - C28 Clock HCLKS Asynchronous AHB Clock In I - A7 Clock nPLLRESET PLL reset I - H7 Clock PLLCLKEXT Clock input from a PLL I - F8 Clock PLLPWRDN PLL power down I - D3 Clock REFCLK32K 32KHz Reference Clock I - C5 Clock TIMCLKEXT Time
Signals on Pads Table A-1 Pad signals (continued) A-16 Function Signal Description Type Drive BGA DMAC DMACLBREQ[0] Last Burst Transfer Request I - N1 DMAC DMACLBREQ[1] Last Burst Transfer Request I - U5 DMAC DMACLBREQ[2] Last Burst Transfer Request I - P4 DMAC DMACLBREQ[3] Last Burst Transfer Request I - U7 DMAC DMACLBREQ[4] Last Burst Transfer Request I - P3 DMAC DMACLBREQ[5] Last Burst Transfer Request I - V5 DMAC DMACLSREQ[0] Last Single Transfer Request I
Signals on Pads Table A-1 Pad signals (continued) Function Signal Description Type Drive BGA ETM ETMEXTOUT[0] Debug cross trigger support O 12 A14 ETM ETMEXTOUT[1] Debug cross trigger support O 12 B14 ETM ETMEXTOUT[2] Debug cross trigger support O 12 D14 ETM ETMEXTOUT[3] Debug cross trigger support O 12 A13 ETM PIPESTAT[0] Pipeline Status O 12 C18 ETM PIPESTAT[1] Pipeline Status O 12 F17 ETM PIPESTAT[2] Pipeline Status O 12 B18 ETM TRACECLK Trace Clock O
Signals on Pads Table A-1 Pad signals (continued) A-18 Function Signal Description Type Drive BGA GPIO 0 GP0[1] General Purpose I/O B 8 AJ5 GPIO 0 GP0[2] General Purpose I/O B 8 AF7 GPIO 0 GP0[3] General Purpose I/O B 8 AH6 GPIO 0 GP0[4] General Purpose I/O B 8 AK1 GPIO 0 GP0[5] General Purpose I/O B 8 AK2 GPIO 0 GP0[6] General Purpose I/O B 8 AG5 GPIO 0 GP0[7] General Purpose I/O B 8 AK3 GPIO 1 GP1[0] General Purpose I/O B 4 AG6 GPIO 1 GP1[1] Gener
Signals on Pads Table A-1 Pad signals (continued) Function Signal Description Type Drive BGA GPIO 3 GP3[2] General Purpose I/O B 4 AL6 GPIO 3 GP3[3] General Purpose I/O B 4 AK9 GPIO 3 GP3[4] General Purpose I/O B 4 AM6 GPIO 3 GP3[5] General Purpose I/O B 4 AH10 GPIO 3 GP3[6] General Purpose I/O B 4 AN6 GPIO 3 GP3[7] General Purpose I/O B 4 AJ10 JTAG nBSTAPEN Boundary Scan TAP Select IPU - C21 JTAG nTRST Test Reset IPU - D21 JTAG RTCK Sync of Multi-ICE
Signals on Pads Table A-1 Pad signals (continued) A-20 Function Signal Description Type Drive BGA MPMC MPMCADDR[5] Address bus O 12 AA4 MPMC MPMCADDR[6] Address bus O 12 AA6 MPMC MPMCADDR[7] Address bus O 12 AB1 MPMC MPMCADDR[8] Address bus O 12 AA7 MPMC MPMCADDR[9] Address bus O 12 AB2 MPMC MPMCADDR[10] Address bus O 12 AB3 MPMC MPMCADDR[11] Address bus O 12 AC1 MPMC MPMCADDR[12] Address bus O 12 AB5 MPMC MPMCADDR[13] Address bus O 12 AC2 MPMC
Signals on Pads Table A-1 Pad signals (continued) Function Signal Description Type Drive BGA MPMC MPMCDATA[6] Data bus B 8 AD4 MPMC MPMCDATA[7] Data bus B 8 AC5 MPMC MPMCDATA[8] Data bus B 8 AE2 MPMC MPMCDATA[9] Data bus B 8 AC6 MPMC MPMCDATA[10] Data bus B 8 AE3 MPMC MPMCDATA[11] Data bus B 8 AF1 MPMC MPMCDATA[12] Data bus B 8 AF2 MPMC MPMCDATA[13] Data bus B 8 AC7 MPMC MPMCDATA[14] Data bus B 8 AF3 MPMC MPMCDATA[15] Data bus B 8 AD6 MPMC
Signals on Pads Table A-1 Pad signals (continued) A-22 Function Signal Description Type Drive BGA MPMC MPMCDATA[31] Data bus B 8 AE7 MPMC MPMCDQM[0] Data mask & byte lane select O 8 V2 MPMC MPMCDQM[1] Data mask & byte lane select O 8 W7 MPMC MPMCDQM[2] Data mask & byte lane select O 8 V4 MPMC MPMCDQM[3] Data mask & byte lane select O 8 Y5 MPMC MPMCFBCLK Clock feedback I - U4 MPMC MPMCRPVHHOUT Select Vh level for nRP O 4 AF5 MPMC nMPMCCAS Column address st
Signals on Pads Table A-1 Pad signals (continued) Function Signal Description Type Drive BGA Power VDDC[6] Core Power PC - AH3 Power VDDC[7] Core Power PC - AP6 Power VDDC[8] Core Power PC - AP9 Power VDDC[9] Core Power PC - AN12 Power VDDC[10] Core Power PC - AP20 Power VDDC[11] Core Power PC - AP21 Power VDDC[12] Core Power PC - AM24 Power VDDC[13] Core Power PC - AM27 Power VDDC[14] Core Power PC - AJ34 Power VDDC[15] Core Power PC - AE32
Signals on Pads Table A-1 Pad signals (continued) A-24 Function Signal Description Type Drive BGA Power VDDIO[3] I/O Power PIO - AL1 Power VDDIO[4] I/O Power PIO - AN1 Power VDDIO[5] I/O Power PIO - A2 Power VDDIO[6] I/O Power PIO - C2 Power VDDIO[7] I/O Power PIO - AM2 Power VDDIO[8] I/O Power PIO - AP2 Power VDDIO[9] I/O Power PIO - B3 Power VDDIO[10] I/O Power PIO - AN3 Power VDDIO[11] I/O Power PIO - A4 Power VDDIO[12] I/O Power PIO - D
Signals on Pads Table A-1 Pad signals (continued) Function Signal Description Type Drive BGA Power VDDIO[28] I/O Power PIO - D19 Power VDDIO[29] I/O Power PIO - AL19 Power VDDIO[30] I/O Power PIO - D22 Power VDDIO[31] I/O Power PIO - AL22 Power VDDIO[32] I/O Power PIO - D25 Power VDDIO[33] I/O Power PIO - AL25 Power VDDIO[34] I/O Power PIO - E30 Power VDDIO[35] I/O Power PIO - AK30 Power VDDIO[36] I/O Power PIO - A31 Power VDDIO[37] I/O Power P
Signals on Pads Table A-1 Pad signals (continued) A-26 Function Signal Description Type Drive BGA Power VDDIO[53] I/O Power PIO - D34 Power VDDIO[54] I/O Power PIO - U34 Power VDDIO[55] I/O Power PIO - AL34 Power VDDIO[56] I/O Power PIO - AN34 Smart Card nSCICARDRST Card reset O 4 R30 Smart Card nSCICLKEN Tristate buffer control O 4 P32 Smart Card nSCIDATAEN Tristate buffer control O 4 T29 Smart Card nSCIDATAOUTEN Serial data buffer control O 4 P33 Sm
Signals on Pads Table A-1 Pad signals (continued) Function Signal Description Type Drive BGA SSMC nSTATICCS[2] Chip select O 8 AN20 SSMC nSTATICCS[3] Chip select O 8 AM20 SSMC nSTATICCS[4] Chip select O 8 AL20 SSMC nSTATICCS[5] Chip select O 8 AJ18 SSMC nSTATICCS[6] Chip select O 8 AN21 SSMC nSTATICCS[7] Chip select O 8 AK19 SSMC SMADDR[0] Address bus O 12 AH15 SSMC SMADDR[1] Address bus O 12 AM14 SSMC SMADDR[2] Address bus O 12 AJ15 SSMC SMADDR[
Signals on Pads Table A-1 Pad signals (continued) A-28 Function Signal Description Type Drive BGA SSMC SMADDR[19] Address bus O 12 AN17 SSMC SMADDR[20] Address bus O 12 AK16 SSMC SMADDR[21] Address bus O 12 AP18 SSMC SMADDR[22] Address bus O 12 AN18 SSMC SMADDR[23] Address bus O 12 AL18 SSMC SMADDR[24] Address bus O 12 AJ17 SSMC SMADDR[25] Address bus O 12 AM18 SSMC SMADDRVALID Address valid O 8 AK18 SSMC SMBAA Burst address advance O 8 AN19 SSM
Signals on Pads Table A-1 Pad signals (continued) Function Signal Description Type Drive BGA SSMC SMDATA[12] Data bus B 8 AK12 SSMC SMDATA[13] Data bus B 8 AN10 SSMC SMDATA[14] Data bus B 8 AH13 SSMC SMDATA[15] Data bus B 8 AP10 SSMC SMDATA[16] Data bus B 8 AL11 SSMC SMDATA[17] Data bus B 8 AM11 SSMC SMDATA[18] Data bus B 8 AK13 SSMC SMDATA[19] Data bus B 8 AN11 SSMC SMDATA[20] Data bus B 8 AJ13 SSMC SMDATA[21] Data bus B 8 AP11 SSMC SMDATA
Signals on Pads Table A-1 Pad signals (continued) A-30 Function Signal Description Type Drive BGA SSP SSPCLKIN Clock input I - C20 SSP SSPCLKOUT Clock output O 4 G18 SSP SSPFSSIN Frame input I - D20 SSP SSPFSSOUT Frame or slave select O 4 F18 SSP SSPRXD Receive data input I - E19 SSP SSPTXD Transmit data output O 4 B20 UART 0 nSIROUT0 SIR transmitted serial data O 4 AJ28 UART 0 nUART0CTS Clear to send I - AH25 UART 0 nUART0DCD Data Carrier detect I
Signals on Pads Table A-1 Pad signals (continued) Function Signal Description Type Drive BGA UART 2 UART2RXD Received serial data I - AJ29 UART 2 UART2TXD Transmitted serial data O 4 AH28 VIC PWRFAIL Interrupt source I - AL27 VIC VICINTSOURCE[21] Interrupt source I - AJ24 VIC VICINTSOURCE[22] Interrupt source I - AP28 VIC VICINTSOURCE[23] Interrupt source I - AN28 VIC VICINTSOURCE[24] Interrupt source I - AM28 VIC VICINTSOURCE[25] Interrupt source I - AH
Signals on Pads A-32 Copyright © 2004, 2006 ARM Limited. All rights reserved.
Appendix B Mechanical and Electrical Specifications This appendix contains the specifications. It contains the following sections: • Mechanical details on page B-2 • Electrical specification on page B-3. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
Mechanical and Electrical Specifications B.1 Mechanical details Figure B-1 shows the pad numbering. Power and ground pins are highlighted. The ball spacing is 1mm.
Mechanical and Electrical Specifications B.2 Electrical specification This section provides details of the voltage and current characteristics for the core module. B.2.1 Bus interface characteristics Table B-1 shows the core module electrical characteristics for the system bus interface. Table B-1 Interface signal electrical characteristics Symbol Description Min Max VIH High-level input voltage 2.0V 3.6V VIL Low-level input voltage 0V 0.8V VOH High-level output voltage 2.
Mechanical and Electrical Specifications B.2.2 Power estimation Table B-3 shows the maximum power requirements. Table B-3 Power estimate B.2.3 Description Power Total Logic, RAM and Clock Tree Power 1W Total I/O Power 3.5W Total 4.5 W Power sequencing There is an internal parasitic diode path from core voltage to I/O voltage. If the lower core voltage is powered up earlier than the higher I/O voltage, current flow through the parasitic diode can cause latchup.
Appendix C Timing Specification This appendix provides the AC timing parameters for the ARM926EJ-S Development Chip components. It contains the following sections: • About the timing parameters on page C-2 • AHB bus timing on page C-3 • Memory timing on page C-4 • Peripheral timing on page C-5. ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved.
Timing Specification C.1 About the timing parameters Figure C-1 shows the parameters that define the setup and hold times. For more detail on timing and example waveforms, see the TRM for the peripheral. Reference clock tcyc (max) Output signals from ARM926EJ-S Dev. Chip tov (max) toh (min) Input signals to ARM926EJ-S Dev. Chip tis (min) tih (min) Figure C-1 AC timing example The following timing parameters are used: tcyc The maximum cycle time for the clock signal.
Timing Specification C.2 AHB bus timing Table C-1 lists the timing for the AHB buses. (The bus clock frequency is typically 35MHz for a tcyc of 28.5ns).
Timing Specification C.3 Memory timing Table C-2 shows the memory timing. For more detail on timing and example waveforms, see the ARM PrimeCell Static Memory Controller (PL093) Technical Reference Manual and the ARM PrimeCell Multiport Memory Controller (GX175) Technical Reference Manual.
Timing Specification C.4 Peripheral timing Table C-3 shows the peripheral and controller timing. For more detail on timing and example waveforms, see the relevant Technical Reference Manual for the module. Table C-3 Peripherals and controller timing Peripheral signals Clock tov toh tis tih CLCDC outputs (CLD[23:0], CLPOWER, CLLP, CLCP, CLFP, CLAC, and CLLE) CLCDCLK 12.5ns -2.
Timing Specification C-6 Copyright © 2004, 2006 ARM Limited. All rights reserved.
Index The items in this index are listed in alphabetical order, with symbols and numerics appearing at the end. The references given are to page numbers.
Index SCI 12-6 signals 2-32 SSMC 13-9 SSP 14-4 Watchdog 19-3 Core DMA APB 3-3 Current requirements B-4 D DMA APB base address 3-30 support 1-13 DMA APB 3-3 DMAC 1-6 features 8-2 interrupt source 8-5 master interfaces 8-5 pad signals 8-7 peripheral request lines 8-5 DOZE mode 2-7, 2-10 Dynamic memory 10-4 E Electrical characteristics B-3 Embedded Trace Macrocell 1-6 Endianness 3-14 ETM9 1-6 F FIFO 16-2 FIQ 17-2 Frame synchronization 5-23 G GPIO features 9-2 pad signals 9-5 Index-2 H Hardware cursor cu
Index R RTC 1-6 base address 11-4 input clock 11-2 reserved locations 11-4 RTCINTR interrupt 11-4 S SCI 1-4, 1-8 base address 12-4 interrupts 12-5 pad signals 12-6 programmable parameters 12-3 timing C-5 SDRAM low power modes 2-17 operating frequency 2-17 Signals AHBMONITOR 4-3 BATOK 2-4 BIGENDOUT 3-14 CFGAHBM1ASYNC 2-22 CFGAHBM2ASYNC 2-22 CFGAHBSASYNC 2-23 CFGBRIDGEMEMMAP 3-15 CFGCPUBIGENDIN 2-20 CFGCPUVINITHI 2-20 CFGHCLKDIVSEL 2-21 CFGHCLKEXTDIVSEL 2-22 CFGMBXCLKDIVSEL 2-22 CFGMCCLKDIVSEL 2-22 CFGMPMCn
Index pin numbering B-2 SSMC 1-5 features 13-2 I/O connections 13-5 pad signals 13-9, A-1 SSP Features 14-2 Interrupts 14-5 pad signals 14-6 timing C-5 Static memory devices supported 10-5 Support code IEEE 754 standard compliance 18-2 RunFast mode 18-2, 18-8 subnormal input 18-6 Supported dynamic memory devices 10-4 SynchFlash devices 10-4 System controller 1-5 core clock control 2-12 HCLK to CLK relationship 2-12 interrupt response mode 2-3 low battery handling 2-4 modes 2-7 operation 2-13 pad signals 2-
