Product data

LPC3130_3131 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 May 2012 54 of 67
NXP Semiconductors
LPC3130/3131
Low-cost, low-power ARM926EJ-S microcontrollers
9.4 NAND flash memory controller
[1] T
HCLK
= 1/NANDFLASH_NAND_CLK, see LPC3130/3131 user manual.
[2] See registers NandTiming1 and NandTiming2 in the LPC3130/3131 user manual.
[3] Each timing parameter can be set from 7 nand_clk clock cycles to 1 nand_clk clock cycle. (A programmed
zero value is treated as a one).
Table 20. Dynamic characteristics of the NAND flash memory controller
T
amb
=  40  C to +85  C, unless otherwise specified.
Symbol Parameter Typical Unit
t
REH
RE HIGH hold time
[1][2][3]
T
HCLK
 (TREH) ns
t
RP
RE pulse width
[1][2][3]
T
HCLK
 (TRP) ns
t
WH
WE HIGH hold time
[1][2][3]
T
HCLK
 (TWH) ns
t
WP
WE pulse width
[1][2][3]
T
HCLK
 (TWP) ns
t
CLS
CLE set-up time
[1][2][3]
T
HCLK
 (TCLS) ns
t
CLH
CLE hold time
[1][2][3]
T
HCLK
 (TCLH) ns
t
ALS
ALE set-up time
[1][2][3]
T
HCLK
 (TALS) ns
t
ALH
ALE hold time
[1][2][3]
T
HCLK
 (TALH) ns
t
CS
CE set-up time
[1][2][3]
T
HCLK
 (TCS) ns
t
CH
CE hold time
[1][2][3]
T
HCLK
 (TCH) ns
Fig 18. NAND flash controller write and read timing
EBI_NWE
EBI_A_1_CLE
EBI_A_0_ALE
t
WP
t
CS
t
CH
t
CLS
t
CLH
mNAND_NCS
t
WH
002aae353
t
ALS
t
ALH
t
RP
t
REH
EBI_DQM_0_NOE