Product data

LPC3130_3131 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 May 2012 51 of 67
NXP Semiconductors
LPC3130/3131
Low-cost, low-power ARM926EJ-S microcontrollers
9.3 SDRAM controller
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] All values valid for pads set to high slew rate. VDDE_IOA = VDDE_IOB = 1.8  0.15 V. VDDI = 1.2  0.1 V.
[3] Refer to the LPC3130/3131 user manual for the programming of MPMCDynamicReadConfig and SYSCREG_MPMP_DELAYMODES
registers.
[4] f
oper
= 1 / T
CLCL
[5] t
d(o)
, t
h(o)
, t
d(AV)
, t
h(A)
, t
d(QV)
, t
h(Q)
times are dependent on MPMCDynamicReadConfig register value and
SYSCREG_MPMP_DELAYMODES register bits 11:6.
Table 19. Dynamic characteristics of SDR SDRAM memory interface
T
amb
=  40  C to +85  C, unless otherwise specified; V
DD(IO)
= 1.8 V and 3.3 V (SUP8).
[1][2][3]
Symbol Parameter Conditions Min Typical Max Unit
f
oper
operating frequency
[4]
-80 90 MHz
t
CLCX
clock LOW time - 5.55 - ns
t
CHCX
clock HIGH time - 5.55 - ns
t
d(o)
output delay time on pin EBI_CKE
[5]
-- 3.6 ns
on pins
EBI_NRAS_BLOUT,
EBI_NCAS_BLOUT,
EBI_NWE,
EBI_NDYCS
-- 3.6 ns
on pins EBI_DQM_1,
EBI_DQM_0_NOE
-- 5 ns
t
h(o)
output hold time on pin EBI_CKE
[5]
0.13 - 3.6 ns
on pins
EBI_NRAS_BLOUT,
EBI_NCAS_BLOUT,
EBI_NWE,
EBI_NDYCS
0.1 - 3.6 ns
on pins EBI_DQM_1,
EBI_DQM_0_NOE
1.7 - 5 ns
t
d(AV)
address valid delay
time
[5]
-- 5 ns
t
h(A)
address hold time
[5]
0.1 - 5 ns
t
d(QV)
data output valid
delay time
[5]
-- 9 ns
t
h(Q)
data output hold time
[5]
4- 10 ns
t
QZ
data output
high-impedance time
-- <T
CLCL
ns