Product data

LPC3130_3131 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 May 2012 49 of 67
NXP Semiconductors
LPC3130/3131
Low-cost, low-power ARM926EJ-S microcontrollers
[4] One HCLK cycle delay added when SYSCREG_MPMC_WAITREAD_DELAYx register bit 5 = 1.
[5] WAITRD must  to WAITOEN for there to be any delay between CS
active and BLS active. The maximum delay is limited to (WAITRD *
HCLK).
[6] There is one less HCLK cycle when SYSCREG_MPMC_WAITREAD_DELAYx bit 5 = 1.
[7] The MPMC will ensure a minimum of one HCLK for this parameter.
[8] This formula applies when WAITWR is  WAITWEN. One HCLK cycle minimum.
[9] This formula applies when WAITWR is  WAITWEN.
[10] This formula applies when WAITWR is  WAITWEN. Data valid minimum One HCLK cycle before WE
goes active.
[11] This formula applies when WAITWR is  WAITWEN. Three HCLK cycles minimum.
[12] Refer to the LPC3130/3131 user manual for the programming of WAITRD and HCLK.
[13] Refer to the LPC3130/3131 user manual for the programming of WAITWEN and HCLK.
[14] Refer to the LPC3130/3131 user manual for the programming of WAITWR and HCLK.
Fig 14. External memory read access to static memory
t
CSHOEH
t
CSHBLSH
t
OEHANV
t
BLSHANV
t
CSLOEL
t
OELOEH
t
CSLBLSL
t
BLSLBLSH
t
CSLAV
t
OELAV
t
BLSLAV
t
h(DQ)
t
su(DQ)
EBI_NSTCS_X
EBI_DQM_0_NOE
EBI_NCAS_BLOUT_0
EBI_NRAS_BLOUT_1
EBI_A_[15:0]
EBI_D_[15:0]
002aae161