Product data

LPC3130_3131 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 May 2012 48 of 67
NXP Semiconductors
LPC3130/3131
Low-cost, low-power ARM926EJ-S microcontrollers
9.2 SRAM controller
[1] Refer to the LPC3130/3131 user manual for the programming of WAITOEN and HCLK.
[2] Only when WAITRD is  to WAITOEN, otherwise OE
, CS, BLS and Address will change state about the same time.
[3] WAITRD must  to WAITOEN for there to be any delay between CS
active and OE active. The maximum delay is limited to (WAITRD *
HCLK).
Table 18. Dynamic characteristics: static external memory interface
C
L
=25pF, T
amb
=  40  C to +85  C, unless otherwise specified; V
DD(IO)
= 1.8 V and 3.3 V (SUP8).
Symbol Parameter Conditions Min Typ Max Unit
Common to read and write cycles
t
CSLAV
CS LOW to address valid
time
1.8 0 4 ns
Read cycle parameters
t
OELAV
OE LOW to address valid
time
[1][2]
-0 WAITOEN  HCLK - ns
t
BLSLAV
BLS LOW to address valid
time
[1][2]
-0 WAITOEN  HCLK - ns
t
CSLOEL
CS LOW to OE LOW time
[3][4]
- 0 + WAITOEN  HCLK - ns
t
CSLBLSL
CS LOW to BLS LOW time
[1][5]
- 0 + WAITOEN  HCLK - ns
t
OELOEH
OE LOW to OE HIGH time
[1][6][7]
[12]
-(WAITRD WAITOEN + 1)  HCLK - ns
t
BLSLBLSH
BLS LOW to BLS HIGH time
[1][7]
[12]
-(WAITRD WAITOEN + 1)  HCLK - ns
t
su(D)
data input set-up time 9 - - ns
t
h(D)
data input hold time - 0 - ns
t
CSHOEH
CS HIGH to OE HIGH time 3 0 - ns
t
CSHBLSH
CS HIGH to BLS HIGH time - 0 - ns
t
OEHANV
OE HIGH to address invalid
time
10 - - ns
t
BLSHANV
BLS HIGH to address invalid
time
-1 HCLK - ns
Write cycle parameters
t
CSLDV
CS LOW to data valid time - - 9 ns
t
CSLWEL
CS LOW to WE LOW time
[8][13]
-(WAITWEN+1) HCLK - ns
t
CSLBLSL
CS LOW to BLS LOW time
[9][13]
- WAITWEN  HCLK - ns
t
WELDV
WE LOW to data valid time
[10][13]
-0 (WAITWEN + 1)  HCLK - ns
t
WELWEH
WE LOW to WE HIGH time
[7][8]
[13][14]
-(WAITWR WAITWEN + 1)  HCLK - ns
t
BLSLBLSH
BLS LOW to BLS HIGH time
[11][13]
[14]
-(WAITWR WAITWEN + 3)  HCLK - ns
t
WEHANV
WE HIGH to address invalid
time
-1 HCLK - ns
t
WEHDNV
WE HIGH to data invalid time - 1  HCLK - ns
t
BLSHANV
BLS HIGH to address invalid
time
-1 HCLK - ns
t
BLSHDNV
BLS HIGH to data invalid
time
-1 HCLK - ns