Product data

LPC3130_3131 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 May 2012 46 of 67
NXP Semiconductors
LPC3130/3131
Low-cost, low-power ARM926EJ-S microcontrollers
9.1.2 Motorola 6800 mode
[1] Timing is derived from the LCD Interface Control Register fields: INVERT_CS = 1; MI = 1; PS = 0;
INVERT_E_RD = 0. See LPC3130/3131 user manual.
Table 16. Dynamic characteristics: LCD controller in Motorola 6800 mode
C
L
=25pF, T
amb
=  40  C to +85  C, unless otherwise specified; V
DD(IO)
= 1.8 V and 3.3 V (SUP8).
Symbol Parameter Conditions Min Typ Max Unit
t
su(A)
address set-up time - 1  LCDCLK - ns
t
h(A)
address hold time - 2  LCDCLK - ns
t
cy(a)
access cycle time
[1]
-5  LCDCLK - ns
t
r
rise time 2 - 5 ns
t
f
fall time 2 - 5 ns
t
d(QV)
data output valid delay time - 1  LCDCLK - ns
t
dis(Q)
data output disable time - 2  LCDCLK - ns
t
w(en)
enable pulse width read cycle - 2  LCDCLK - ns
write cycle - 2  LCDCLK - ns
Fig 12. LCD timing (Motorola 6800 mode)
002aae208
mLCD_CSB
mLCD_E_RD
mLCD_RS,
mLCD_RW_WR
mLCD_DB[15:0] (16 bit mode),
mLCD_DB[15:8] (8 bit mode),
mLCD_DB[15:12] (4 bit mode)
mLCD_DB[15:0] (16 bit mode),
mLCD_DB[15:8] (8 bit mode),
mLCD_DB[15:12] (4 bit mode)
t
su(D)
t
d(QV)
t
su(A)
t
h(A)
t
h(D)
t
f
t
r
write access
read access
t
dis(Q)
t
w(en)
t
cy(a)