Product data

LPC3130_3131 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 May 2012 35 of 67
NXP Semiconductors
LPC3130/3131
Low-cost, low-power ARM926EJ-S microcontrollers
6.29 System control registers
The System Control Registers (SysCReg) module provides a register interface for some
of the high-level settings in the system such as multiplexers and mode settings. This is an
auxiliary module included in this overview for the sake of completeness.
6.30 I2S0/1 interfaces
The I2S0/1 receive and I2S0/1 transmit modules have the following features:
• Audio interface compatible with the I
2
S standard.
• I2S0/1 receive supports master mode and slave mode.
• I2S0/1 transmit supports master mode.
• Supports LSB justified words of 16, 18, 20 and 24 bits.
• Supports a configurable number of bit clock periods per Word Select period (up to
128 bit clock periods).
• Supports DMA transfers.
• Transmit FIFO (I
2
S transmit) or receive FIFO (I
2
S receive) of 4 stereo samples.
• Supports single 16 bit transfers to/from the left or right FIFO.
• Supports single 24 bit transfers to/from the left or right FIFO.
• Supports 32-bit interleaved transfers, with the lower 16 bits representing the left audio
sample, and the higher 16 bits representing the right audio sample.
• Supports two 16-bit audio samples combined in a 32-bit word (2 left or 2 right
samples) to reduce bus load.
• Provides maskable interrupts for audio status: FIFO underrun/overrun/full/
half_full/not empty for left and right channel separately.