Product data

LPC3130_3131 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 May 2012 33 of 67
NXP Semiconductors
LPC3130/3131
Low-cost, low-power ARM926EJ-S microcontrollers
6.26.2 Multiplexing between LCD and MPMC
The multiplexing between the LCD interface and MPMC allows for the following two
modes of operation:
• MPMC-mode: SDRAM and bus-based LCD or SRAM.
• LCD-mode: Dedicated LCD-Interface.
The external NAND flash is accessible in both modes.
The block diagram Figure 9
gives a high level overview of the modules in the chip that are
involved in the pin interface multiplexing between the EBI, NAND flash controller, MPMC,
and RAM-based LCD interface.
Figure 9 only shows the signals that are involved in pad-muxing, so not all interface
signals are visible.
Fig 9. Diagram of LCD and MPMC multiplexing
NAND_RYBN[0:3]
NAND_NCS_[0:3]
NAND
FLASH
INTERFACE
control
control
control
data
LCD_DB_[1:0],
control
control
control
(ALE, CLE)
EBI_A_0_ALE
EBI_A_1_CLE
EBI
2
16
data
2
6
data
16
address
EBI_A_[15:2]
14
14
data
LCD_DB_[15:2]
14
6
EBI_NCAS_BLOUT_0
EBI_NRAS_BLOUT_1
EBI_DQM_0_NOE
LCD_CSB/EBI_NSTCS_0
LCD_DB_1/EBI_NSTCS_1
LCD_DB_0/EBI_CLKOUT
LCD_E_RD/EBI_CKE
LCD_RS/EBI_NDYCS
LCD_RW_WR/EBI_DQM_1
LCD_DB_[15:2] (LCD mode)/
EBI_A_[15:2] (MPMC mode)
EBI_D_[15:0]
16
data
16
address
MPMC
LCD
address
EBI_A_[1:0]
2
6
3
SYSCREG_MUX_LCD_EBI_SEL
register
(I/O multplexing)
MPMC
mode
LCD
mode
LPC31xx
002aae157
SUP4
SUP8
0
1
0
1