Product data

LPC3130_3131 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 May 2012 30 of 67
NXP Semiconductors
LPC3130/3131
Low-cost, low-power ARM926EJ-S microcontrollers
6.25 I
2
C-bus master/slave interface
The LPC3130/3131 contains two I
2
C master/slave interfaces.
This module has the following features:
• I2C-bus interface 0 (I2C0): I2C0 is a standard I
2
C-compliant bus interface with
open-drain pins. This interface supports functions described in the I
2
C-bus
specification for speeds up to 400 kHz. This includes multi-master operation and
allows powering off this device in a working system while leaving the I
2
C-bus
functional.
• I2C-bus interface 1 (I2C1): I2C1 uses standard I/O pins and is intended for use with
a single-master I
2
C-bus and does not support powering off of this device. Standard
I/Os also do not support multi-master I
2
C implementations.
• Supports normal mode (100 kHz SCL).
• Fast mode (400 kHz SCL with 24 MHz APB clock; 325 kHz with12 MHz APB clock;
175 kHz with 6 MHz APB clock).
• Interrupt support.
• Supports DMA transfers (single).
• Four modes of operation:
– Master transmitter
– Master receiver
– Slave transmitter
– Slave receiver
6.26 LCD/NAND flash/SDRAM multiplexing
The LPC3130/3131 contains a rich set of specialized hardware interfaces but the TFBGA
package does not contain enough pins to allow use of all signals of all interfaces
simultaneously. Therefore a pin-multiplexing scheme is created, which allows the
selection of the right interface for the application.
Pin multiplexing is enabled between the following interfaces:
• between the dedicated LCD interface and the external bus interface.
• between the NAND flash controller and the memory card interface.
• between UART and SPI.
• between I2STX_0 output and the PCM interface.
The pin interface multiplexing is subdivided into five categories: storage, video, audio,
NAND flash, and UART related pin multiplexing. Each category supports several modes,
which can be selected by programming the corresponding registers in the SysCReg.