Product data

LPC3130_3131 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 May 2012 21 of 67
NXP Semiconductors
LPC3130/3131
Low-cost, low-power ARM926EJ-S microcontrollers
• Visibility of the interrupt’s request state before masking.
• Support for nesting of interrupt service routines.
• Interrupts routed to IRQ and to FIQ are vectored.
• Level interrupt support.
The following blocks can generate interrupts:
• NAND flash controller
• USB 2.0 high-speed OTG
• Event router
• 10-bit ADC
• UART
• LCD
• MCI
• SPI
• I2C0 and I2C1 controllers
• Timer0, Timer1, Timer2, and Timer3
• I
2
S transmit: I2STX_0 and I2STX_1
• I
2
S receive: I2SRX_0 and I2SRX_1
• DMA
6.13 Multi-layer AHB
The multi-layer AHB is an interconnection scheme based on the AHB protocol that
enables parallel access paths between multiple masters and slaves in a system.
Multiple masters can have access to different slaves at the same time.
Figure 5
gives an overview of the multi-layer AHB configuration in the LPC3130/3131.
AHB masters and slaves are numbered according to their AHB port number.