Product data

LPC3130_3131 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 May 2012 20 of 67
NXP Semiconductors
LPC3130/3131
Low-cost, low-power ARM926EJ-S microcontrollers
– Memory can be copied from the source address to the destination address with a
specified length, while incrementing the address for both the source and
destination.
Memory to peripheral:
– Data is transferred from incrementing memory to a fixed address of a peripheral.
The flow is controlled by the peripheral.
Peripheral to memory:
– Data is transferred from a fixed address of a peripheral to incrementing memory.
The flow is controlled by the peripheral.
• Supports single data transfers for all transfer types.
• Supports burst transfers for memory to memory transfers. A burst always consists of
multiples of 4 (32 bit) words.
• The DMA controller has 12 channels.
• Scatter-gather is used to gather data located at different areas of memory. Two
channels are needed per scatter-gather action.
• Supports byte, half word and word transfers, and correctly aligns it over the AHB bus.
• Compatible with ARM flow control for single requests (sreq), last single requests
(lsreq), terminal count info (tc), and dma clearing (clr).
• Supports swapping in endianess of the transported data.
6.12 Interrupt controller (INTC)
The interrupt controller collects interrupt requests from multiple devices, masks interrupt
requests, and forwards the combined requests to the processor. The interrupt controller
also provides facilities to identify the interrupt requesting devices to be served.
This module has the following features:
• The interrupt controller decodes all the interrupt requests issued by the on-chip
peripherals.
• Two interrupt lines (Fast Interrupt Request (FIQ), Interrupt Request (IRQ)) to the ARM
core. The ARM core supports two distinct levels of priority on all interrupt sources,
FIQ for high priority interrupts and IRQ for normal priority interrupts.
• Software interrupt request capability associated with each request input.
Table 9: Peripherals that support DMA access
Peripheral name Supported Transfer Types
NAND flash controller Memory to memory
SPI Memory to peripheral and peripheral to memory
MCI Memory to peripheral and peripheral to memory
LCD interface Memory to peripheral
UART Memory to peripheral and peripheral to memory
I2C0/1-bus master/slave Memory to peripheral and peripheral to memory
I2S0/1 receive Peripheral to memory
I2S0/1 transmit Memory to peripheral
PCM interface Memory to peripheral and peripheral to memory