Product data
LPC3130_3131 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 May 2012 17 of 67
NXP Semiconductors
LPC3130/3131
Low-cost, low-power ARM926EJ-S microcontrollers
– extended wait
• One chip select for synchronous memory and two chip selects for static memory
devices.
• Power-saving modes.
• Dynamic memory self-refresh mode supported.
• Controller support for 2 k, 4 k, and 8 k row address synchronous memory parts.
• Support for all AHB burst types.
• Little and big-endian support.
• Support for the External Bus Interface (EBI) that enables the memory controller pads
to be shared.
6.6 External Bus Interface (EBI)
The EBI module acts as multiplexer with arbitration between the NAND flash and the
SDRAM/SRAM memory modules connected externally through the MPMC.
The main purpose for using the EBI module is to save external pins. However only data
and address pins are multiplexed. Control signals towards and from the external memory
devices are not multiplexed.
6.7 Internal ROM Memory
The internal ROM memory is used to store the boot code of the LPC3130/3131. After a
reset, the ARM processor will start its code execution from this memory.
The LPC3130/3131 ROM memory has the following features:
• Supports booting from SPI flash, NAND flash, SD/SDHC/MMC cards, UART, and
USB (DFU class) interfaces.
• Supports option to perform CRC32 checking on the boot image.
• Supports booting from managed NAND devices such as moviNAND, iNAND,
eMMC-NAND and eSD-NAND using SD/MMC boot mode.
• Contains pre-defined MMU table (16 kB) for simple systems.
The boot ROM determines the boot mode based on reset state of GPIO0, GPIO1, and
GPIO2 pins. To ensure that GPIO0, GPIO1 and GPIO2 pins come up as inputs, pins
TRST_N and JTAGSEL must be LOW during power-on reset (see UM10314 JTAG
chapter for details). Table 8
shows the various boot modes supported on the
LPC3130/3131:
Table 7. Memory map of the external SRAM/SDRAM memory modules
Module Maximum address space Data width Device size
External SRAM0 0x2000 0000 0x2000 FFFF 8 bit 64 kB
0x2000 0000 0x2001 FFFF 16 bit 128 kB
External SRAM1 0x2002 0000 0x2002 FFFF 8 bit 64 kB
0x2002 0000 0x2003 FFFF 16 bit 128 kB
External SDRAM0 0x3000 0000 0x37FF FFFF 16 bit 128 MB