Product data

Product data sheet Rev. 2 — 29 May 2012 15 of 67

NXP Semiconductors

LPC3130/3131

Low-cost, low-power ARM926EJ-S microcontrollers

6.3 JTAG

The Joint Test Action Group (JTAG) interface allows the incorporation of the

LPC3130/3131 in a JTAG scan chain.

This module has the following features:

• ARM926 debug access

• Boundary scan

6.4 NAND flash controller

The NAND flash controller is used as a dedicated interface to NAND flash devices.

Figure 4

shows a block diagram of the NAND flash controller module. The heart of the

module is formed by a controller block that controls the flow of data from/to the AHB bus

through the NAND flash controller block to/from the (external) NAND flash. An error

correction encoder/decoder (ECC enc/dec) module allows for hardware error correction

for support of Multi-Level Cell (MLC) NAND flash devices.

Before data is written from the buffer to the NAND flash, optionally it is first protected by

an error correction code generated by the ECC module. After data is read from the NAND

flash, the error correction module corrects any errors.

This module has the following features:

• Dedicated NAND flash interface with hardware controlled read and write accesses.

• Wear leveling support with 516 byte mode.

• Software controlled command and address transfers to support wide range of flash

devices.

Fig 4. Block diagram of the NAND flash controller

002aae127

AHB MULTILAYER MATRIX

BUFFER

CONTROLLER

ECC

ENCODER/

DECODER

NAND INTERFACE

DMA transfer request