Product data

LPC3130_3131 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 May 2012 12 of 67
NXP Semiconductors
LPC3130/3131
Low-cost, low-power ARM926EJ-S microcontrollers
[5] The UART flow control lines (mUART_CTS_N and mUART_RTS_N) are multiplexed. This means that if these balls are not required for
UART flow control, they can also be selected to be used for an alternative function: SPI chip select signals (SPI_CS_OUT1 and
SPI_CS_OUT2).
[6] To ensure that GPIO0, GPIO1 and GPIO2 pins come up as inputs, pins TRST_N and JTAGSEL must be LOW at power-on reset, see
UM10314 JTAG chapter for details.
[1] When the SDRAM is used, the supply voltage of the NAND flash, SDRAM, and the LCD Interface must be the same, i.e. SUP4 and
SUP8 should be connected to the same rail. (See also Section 6.26.3
.)
Table 5. Supply domains
Supply
domain
Voltage range Related supply pins Description
SUP1 1.0 V to 1.3 V VDDI, VDDA12, USB_VDDA12_PLL Digital core supply
SUP3 2.7 V to 3.6 V VDDE_IOC, ADC10B_VDDA33,
USB_VDDA33_DRV, USB_VDDA33
Peripheral supply
SUP4 1.65 V to 1.95 V (in 1.8 V mode)
2.5 V to 3.6 V (in 3.3 V mode)
VDDE_IOA Peripheral supply for NAND flash
interface
SUP5 4.5 V to 5.5 V USB_VBUS USB VBUS voltage
SUP8 1.65 V to 1.95 V (in 1.8 V mode)
2.5 V to 3.6 V (in 3.3 V mode)
VDDE_IOB Peripheral supply for
SDRAM/SRAM/bus-based LCD
[1]
Table 6: I/O pads
Cell type Pad type Function Description
DIO1 bspts3chp Digital Input/Output Bidirectional 3.3 V; 3-state output; 3 ns slew rate control; plain
input; CMOS with hysteresis; programmable pull-up, pull-down,
repeater
DIO2 bpts5pcph Digital Input/Output Bidirectional 5 V; plain input; 3-state output; CMOS with
programmable hysteresis; programmable pull-up, pull-down,
repeater
DIO4 mem1
bsptz40pchp
Digital Input/Output Bidirectional 1.8 V or 3.3 V; plain input; 3-state output;
programmable hysteresis; programmable pull-up, pull-down,
repeater
IICC iic3m4scl Digital Input/Output I
2
C-bus; clock signal
IICD iic3mvsda Digital Input/Output I
2
C-bus; data signal
AIO1 apio3v3 Analog Input/Output Analog input/output; protection to external 3.3 V supply rail
AIO2 apio Analog Input/Output Analog input/output
AIO3 apiot5v Analog Input/Output Analog input/output; 5 V tolerant pad-based ESD protection
CS1 vddco Core Supply -
CS2 vddi Core Supply -
PS1 vdde3v3 Peripheral Supply -
PS2 vdde Peripheral Supply -
CG1 vssco Core Ground -
CG2 vssis Core Ground -
PG1 vsse Peripheral Ground -