Product data

LPC3130_3131 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 May 2012 11 of 67
NXP Semiconductors
LPC3130/3131
Low-cost, low-power ARM926EJ-S microcontrollers
[1] Digital I/O levels are explained in Table 5.
[2] I = input; I:PU = input with internal weak pull-up; I:PD = input with internal weak pull-down; O = output.
[3] Cell types are explained in Table 6
.
[4] Pin can be configured as GPIO pin in the IOCONFIG block.
External Bus Interface (NAND flash controller)
EBI_A_0_ALE
[4]
B3 SUP4 DO O DIO4 EBI Address Latch Enable
EBI_A_1_CLE
[4]
A2 SUP4 DO O DIO4 EBI Command Latch Enable
EBI_D_0
[4]
G2 SUP4 DIO I DIO4 EBI Data I/O 0
EBI_D_1
[4]
F2 SUP4 DIO I DIO4 EBI Data I/O 1
EBI_D_2
[4]
F1 SUP4 DIO I DIO4 EBI Data I/O 2
EBI_D_3
[4]
E1 SUP4 DIO I DIO4 EBI Data I/O 3
EBI_D_4
[4]
E2 SUP4 DIO I DIO4 EBI Data I/O 4
EBI_D_5
[4]
D1 SUP4 DIO I DIO4 EBI Data I/O 5
EBI_D_6
[4]
D2 SUP4 DIO I DIO4 EBI Data I/O 6
EBI_D_7
[4]
C1 SUP4 DIO I DIO4 EBI Data I/O 7
EBI_D_8
[4]
B1 SUP4 DIO I DIO4 EBI Data I/O 8
EBI_D_9
[4]
A3 SUP4 DIO I DIO4 EBI Data I/O 9
EBI_D_10
[4]
A1 SUP4 DIO I DIO4 EBI Data I/O 10
EBI_D_11
[4]
C2 SUP4 DIO I DIO4 EBI Data I/O 11
EBI_D_12
[4]
G3 SUP4 DIO I DIO4 EBI Data I/O 12
EBI_D_13
[4]
D3 SUP4 DIO I DIO4 EBI Data I/O 13
EBI_D_14
[4]
E3 SUP4 DIO I DIO4 EBI Data I/O 14
EBI_D_15
[4]
F3 SUP4 DIO I DIO4 EBI Data I/O 15
EBI_DQM_0_NOE
[4]
H1 SUP4 DO O DIO4 NAND Read Enable (active LOW)
EBI_NWE
[4]
J2 SUP4 DO O DIO4 NAND Write Enable (active LOW)
NAND_NCS_0
[4]
J1 SUP4 DO O DIO4 NAND Chip Enable 0
NAND_NCS_1
[4]
J3 SUP4 DO O DIO4 NAND Chip Enable 1
NAND_NCS_2
[4]
K1 SUP4 DO O DIO4 NAND Chip Enable 2
NAND_NCS_3
[4]
K2 SUP4 DO O DIO4 NAND Chip Enable 3
mNAND_RYBN0
[4]
E6 SUP4 DI I DIO4 NAND Ready/Busy 0
mNAND_RYBN1
[4]
E7 SUP4 DI I DIO4 NAND Ready/Busy 1
mNAND_RYBN2
[4]
B4 SUP4 DI I DIO4 NAND Ready/Busy 2
mNAND_RYBN3
[4]
D4 SUP4 DI I DIO4 NAND Ready/Busy 3
EBI_NCAS_BLOUT_0
[4]
G1 SUP4 DO O DIO4 EBI Lower lane byte select (7:0)
EBI_NRAS_BLOUT_1
[4]
H2 SUP4 DO O DIO4 EBI Upper lane byte select (15:8)
Pulse Width Modulation module
PWM_DATA
[4]
B9 SUP3 DO / GPIO O DIO1 PWM Output
Table 4. Pin description
Pin names with prefix m are multiplexed pins. See Table 10
for pin function selection of multiplexed pins.
Pin name BGA
ball
Digital
I/O
level
[1]
Application
function
Pin
state
after
reset
[2]
Cell type
[3]
Description