Product data

ManualsBrandsARM ManualsComputer equipmentARM926EJ-S

1. General description

The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB

2.0 On-The-Go (OTG), up to 192 KB SRAM, NAND flash controller, flexible external bus

interface, four channel 10-bit ADC, and a myriad of serial and parallel interfaces in a

single chip targeted at consumer, industrial, medical, and communication markets. To

optimize system power consumption, the LPC3130/3131 have multiple power domains

and a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and

scaling.

2. Features and benefits

2.1 Key features

 CPU platform

 180 MHz, 32-bit ARM926EJ-S

 16 kB D-cache and 16 kB I-cache

 Memory Management Unit (MMU)

 Internal memory

 96 kB (LPC3130) or 192 kB (LPC3131) embedded SRAM

 External memory interface

 NAND flash controller with 8-bit ECC

 8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM

 Communication and connectivity

 High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY

 Two I

S-bus interfaces

 Integrated master/slave SPI

 Two master/slave I

C-bus interfaces

 Fast UART

 Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATA

 Four-channel 10-bit ADC

 Integrated 4/8/16-bit 6800/8080 compatible LCD interface

 System functions

 Dynamic clock gating and scaling

 Multiple power domains

 Selectable boot-up: SPI flash, NAND flash, SD/MMC cards, UART, or USB

 DMA controller

LPC3130/3131

Low-cost, low-power ARM926EJ-S MCUs with high-speed

USB 2.0 OTG, SD/MMC, and NAND flash controller

Rev. 2 — 29 May 2012 Product data sheet

Summary of content (67 pages)

PAGE 1
LPC3130/3131 Low-cost, low-power ARM926EJ-S MCUs with high-speed USB 2.0 OTG, SD/MMC, and NAND flash controller Rev. 2 — 29 May 2012 Product data sheet 1. General description The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB 2.0 On-The-Go (OTG), up to 192 KB SRAM, NAND flash controller, flexible external bus interface, four channel 10-bit ADC, and a myriad of serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, and communication markets.
PAGE 2
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers  Four 32-bit timers  Watchdog timer  PWM module  Random Number Generator (RNG)  General Purpose I/O (GPIO) pins  Flexible and versatile interrupt structure  JTAG interface with boundary scan and ARM debug access  Operating voltage and temperature  Core voltage: 1.2 V  I/O voltage: 1.8 V, 3.3 V  Temperature: 40 C to +85 C  TFBGA180 package: 12  12 mm2, 0.8 mm pitch 3. Ordering information Table 1.
PAGE 3
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 4. Block diagram JTAG interface LPC3130/3131 ARM926EJ-S INSTRUCTION CACHE 16 kB DATA CACHE 16 kB TEST/DEBUG INTERFACE master master USB 2.
PAGE 4
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 5. Pinning information 5.1 Pinning ball A1 index area LPC3130/3131 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D E F G H J K L M N P 002aae130 Transparent top view Fig 2. LPC3130/3131 pinning TFBGA180 package Table 3.
PAGE 5
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers Table 3.
PAGE 6
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers Table 3. Pin allocation table …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol Row P 1 USB_VDDA33 2 USB_DP 3 mLCD_DB_14 4 mLCD_DB_13 5 mLCD_DB_7 6 mLCD_DB_3 7 mLCD_DB_5 8 mLCD_RS 9 mLCD_DB_1 10 TMS 11 I2SRX_WS0 12 UART_RXD 13 TRST_N 14 mUART_RTS_N - - - - Table 4. Pin description Pin names with prefix m are multiplexed pins.
PAGE 7
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers Table 4. Pin description Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins.
PAGE 8
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers Table 4. Pin description Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins.
PAGE 9
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers Table 4. Pin description Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins.
PAGE 10
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers Table 4. Pin description Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins.
PAGE 11
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers Table 4. Pin description Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins.
PAGE 12
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers [5] The UART flow control lines (mUART_CTS_N and mUART_RTS_N) are multiplexed. This means that if these balls are not required for UART flow control, they can also be selected to be used for an alternative function: SPI chip select signals (SPI_CS_OUT1 and SPI_CS_OUT2).
PAGE 13
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 6. Functional description 6.1 ARM926EJ-S The processor embedded in the LPC3130/3131 is the ARM926EJ-S. It is a member of the ARM9 family of general-purpose microprocessors. The ARM926EJ-S is intended for multi-tasking applications where full memory management, high performance, and low power are important.
PAGE 14
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 6.
PAGE 15
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 6.3 JTAG The Joint Test Action Group (JTAG) interface allows the incorporation of the LPC3130/3131 in a JTAG scan chain. This module has the following features: • ARM926 debug access • Boundary scan 6.4 NAND flash controller The NAND flash controller is used as a dedicated interface to NAND flash devices. Figure 4 shows a block diagram of the NAND flash controller module.
PAGE 16
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers • • • • • • Software control mode where the ARM is directly master of the flash device. Support for 8 bit and 16 bit flash devices. Support for any page size from 0.5 kB upwards. Programmable NAND flash timing parameters. Support for up to 4 NAND devices. Error Correction Module (ECC) for MLC NAND flash support: – Reed-Solomon error correction encoding and decoding.
PAGE 17
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers – extended wait • One chip select for synchronous memory and two chip selects for static memory devices. • • • • • • Power-saving modes. Dynamic memory self-refresh mode supported. Controller support for 2 k, 4 k, and 8 k row address synchronous memory parts. Support for all AHB burst types. Little and big-endian support. Support for the External Bus Interface (EBI) that enables the memory controller pads to be shared. 6.
PAGE 18
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers Table 8. LPC3130/3131 boot modes Boot mode GPIO0 GPIO1 GPIO2 Description NAND 0 0 0 Boots from NAND flash. If proper image is not found, boot ROM will switch to DFU boot mode. SPI 0 0 1 Boot from SPI NOR flash connected to SPI_CS_OUT0. If proper image is not found, boot ROM will switch to DFU boot mode. DFU 0 1 0 Device boots via USB using DFU class specification.
PAGE 19
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers • • • • • • • • • • • Supports 1/4-bit SD cards. Card detection and write protection. FIFO buffers of 16 bytes deep. Host pull-up control. SDIO suspend and resume. 1 to 65 535 bytes blocks. Suspend and resume operations. SDIO Read-wait. Maximum clock speed of 52 MHz (MMC 4.1). Supports CE-ATA 1.1. Supports 1-bit, 4-bit, and 8-bit MMC cards and CE-ATA devices. 6.10 High-speed Universal Serial Bus 2.
PAGE 20
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers – Memory can be copied from the source address to the destination address with a specified length, while incrementing the address for both the source and destination. Memory to peripheral: – Data is transferred from incrementing memory to a fixed address of a peripheral. The flow is controlled by the peripheral. Peripheral to memory: – Data is transferred from a fixed address of a peripheral to incrementing memory.
PAGE 21
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers • • • • Visibility of the interrupt’s request state before masking. Support for nesting of interrupt service routines. Interrupts routed to IRQ and to FIQ are vectored. Level interrupt support. The following blocks can generate interrupts: • • • • • • • • • • • • • NAND flash controller USB 2.
PAGE 22
LPC3130/3131 NXP Semiconductors masters 0 ARM 926EJ-S 1 D-CACHE DMA I-CACHE Low-cost, low-power ARM926EJ-S microcontrollers USB-OTG AHB MASTER 2 3 slaves 0 asynchronous bridge AHB-APB BRIDGE 0 0 1 EVENT ROUTER 2 10-bit ADC 3 WDT SYSTEM CONTROL 6 asynchronous bridge 1 AHB-APB BRIDGE 1 asynchronous bridge 2 RNG 0 AHB-APB BRIDGE 2 asynchronous bridge 3 1 TIMER 0 0 1 PCM LCD 0 AHB-APB BRIDGE 3 2 TIMER 1 3 TIMER 2 2 TIMER 3 4 5 IOCONFIG CGU 4 5 PWM I2C0 I2C1 6 3
PAGE 23
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers • Supports all combinations of 32-bit masters and slaves (fully connected interconnect matrix).
PAGE 24
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers Within most clock domains, the output clocks are again grouped into one or more subdomains. All output clocks within one subdomain are either all generated by the same fractional divider or they are connected directly to the base clock. Therefore all output clocks within one subdomain have the same frequency and all output clocks within one clock domain are synchronous because they originate from the same base clock.
PAGE 25
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers • Based on the input of the Watchdog timer (see also Section 6.16), the CGU can generate a system-wide reset in the case of a system stall.
PAGE 26
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers m0 EVENT ROUTER m1 CGU WDT APB INTERRUPT CONTROLLER FIQ IRQ reset 002aae086 Fig 7. Block diagram of the Watchdog timer 6.17 Input/Output configuration module (IOCONFIG) The General Purpose Input/Output (GPIO) pins can be controlled through the register interface provided in the IOCONFIG module.
PAGE 27
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 6.19 Event router The event router extends the interrupt capability of the system by offering a flexible and versatile way of generating interrupts. Combined with the wake-up functionality of the CGU, it also offers a way to wake up the system from suspend mode (with all clocks deactivated).
PAGE 28
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 6.20 Random number generator The Random Number Generator (RNG) generates true random numbers for use in advanced security and Digital Rights Management (DRM) related schemes. These schemes rely upon truly random, i.e. completely unpredictable numbers. This module has the following features: • True random number generator. • The random number register does not rely on any kind of reset.
PAGE 29
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers • SIR-IrDA encoder/decoder (from 2400 to 115 kBd). • Supports maskable interrupts. • Supports DMA transfers. 6.23 Pulse Code Modulation (PCM) interface The PCM interface supports the PCM and IOM interfaces. The IOM (ISDN Oriented Modular) interface is primarily used to interconnect telecommunications ICs providing ISDN compatibility.
PAGE 30
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 6.25 I2C-bus master/slave interface The LPC3130/3131 contains two I2C master/slave interfaces. This module has the following features: • I2C-bus interface 0 (I2C0): I2C0 is a standard I2C-compliant bus interface with open-drain pins. This interface supports functions described in the I2C-bus specification for speeds up to 400 kHz.
PAGE 31
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 6.26.1 Pin connections Table 10. Pin descriptions of multiplexed pins Pin Name Default Signal Alternate Signal Description EBI_NSTCS_0 LCD_CSB — LCD chip select for external LCD controller. Video related pin multiplexing mLCD_CSB LCD_CSB EBI_NSTCS_0 — EBI static memory chip select 0. mLCD_DB_1 LCD_DB_1 EBI_NSTCS_1 LCD_DB_1 — LCD bidirectional data line 1. EBI_NSTCS_1 — EBI static memory chip select 1.
PAGE 32
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers Table 10. Pin descriptions of multiplexed pins …continued Pin Name Default Signal Alternate Signal Description mLCD_DB_15 LCD_DB_15 EBI_A_15 LCD_DB_15 — LCD bidirectional data line 15. EBI_A_15 — EBI address line 15. Storage related pin multiplexing mGPIO5 GPIO5 MCI_CLK GPIO5 — General Purpose I/O pin 5. mGPIO6 GPIO6 MCI_CMD GPIO_6 — General Purpose I/O pin 6. MCI_CLK — MCI card clock.
PAGE 33
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 6.26.2 Multiplexing between LCD and MPMC The multiplexing between the LCD interface and MPMC allows for the following two modes of operation: • MPMC-mode: SDRAM and bus-based LCD or SRAM. • LCD-mode: Dedicated LCD-Interface. The external NAND flash is accessible in both modes.
PAGE 34
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers The EBI unit between the NAND flash interface and the MPMC contains an arbiter that determines which interface is muxed to the outside world. Both NAND flash and SDRAM/SRAM initiate a request to the EBI unit. This request is granted using round-robin arbitration (see Section 6.6). 6.26.
PAGE 35
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 6.29 System control registers The System Control Registers (SysCReg) module provides a register interface for some of the high-level settings in the system such as multiplexers and mode settings. This is an auxiliary module included in this overview for the sake of completeness. 6.
PAGE 36
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 7. Limiting values Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Typ Max Unit All digital I/O pins VI input voltage 0.5 - +3.6 V VO output voltage 0.5 - +3.6 V IO output current - 4 - mA VDDE_IOC = 3.
PAGE 37
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 8. Static characteristics Table 12: Static characteristics Tamb = 40 C to +85 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit input/output supply voltage NAND flash controller pads (SUP4) and LCD interface (SUP8); 1.8 V mode 1.65 1.8 1.95 V NAND flash controller pads (SUP4) and LCD interface (SUP8); 3.3 V mode 2.5 3.3 3.6 V other peripherals (SUP 3) 2.7 3.3 3.
PAGE 38
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers Table 12: Static characteristics Tamb = 40 C to +85 C unless otherwise specified. Symbol Parameter Conditions Ipu pull-up current inputs with pull-up; VI = 0 pull-down current Typ Max Unit SUP4/SUP8; 1.8 V mode [1] 47 65 103 A SUP4/SUP8; 3.3 V mode [1] 45 50 101 A [1] 29 50 76 A SUP4/SUP8; 1.8 V mode [1] 49 75 110 A SUP4/SUP8; 3.
PAGE 39
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers Table 12: Static characteristics Tamb = 40 C to +85 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 0.7VDDE_IOx - - V VIH HIGH-level input voltage [1] VIL LOW-level input voltage [1] - - 0.3VDDE_IOx V Vhys hysteresis voltage [1] 0.1VDDE_IOx - - V VOL LOW-level output voltage IOLS = 3 mA - - 0.
PAGE 40
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers Table 13. ADC static characteristics VDD(ADC) = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified.
PAGE 41
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = VDDA − VSSA 1024 002aac046 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
PAGE 42
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 8.1 Power consumption Table 14. Symbol Power consumption Parameter Standby power IDD P Conditions Min Typ Max Unit core; VDDI = 1.2 V - 1.1 - mA all other SUP1 supplies: VDDA12 = 1.2 V; USB_VDDA12_PL = 1.2 V - 0.175 - mA VDDE_IOA = 1.8 V - 0.001 - mA VDDE_IOB = 1.8 V - 0.0008 - mA VDDE_IOC = 3.3 v - 0.065 - mA ADC10B_VDDA33 = 3.3 V - 0 - mA USB_VDDA33 = 3.
PAGE 43
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers Table 14. Symbol Power consumption …continued Parameter Conditions Min Typ Max Unit External SDRAM based system (operating frequency 180 MHz (core)/ 90 MHz (bus)); normal mode power; without dynamic clock scaling[4] IDD P Supply current Power dissipation core; VDDI = 1.2 V - 33.19 - mA all other SUP1 supplies: VDDA12 = 1.2 V; USB_VDDA12_PL = 1.2 V - 0.93 - mA VDDE_IOA = 1.8 V - 4.
PAGE 44
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers Table 14. Symbol Power consumption …continued Parameter Conditions Min Typ Max Unit Internal SRAM based system (operating frequency 180 MHz (core)/ 90 MHz (bus)); normal mode power; without dynamic clock scaling; MMU off[6] IDD Supply current P Power dissipation core; VDDI = 1.2 V - 26.3 - mA all other SUP1 supplies: VDDA12 = 1.2 V; USB_VDDA12_PL = 1.2 V - 1.57 - mA VDDE_IOA = 1.
PAGE 45
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 9. Dynamic characteristics 9.1 LCD controller 9.1.1 Intel 8080 mode Table 15. Dynamic characteristics: LCD controller in Intel 8080 mode CL = 25 pF, Tamb = 40 C to +85 C, unless otherwise specified; VDD(IO) = 1.8 V and 3.3 V (SUP8).
PAGE 46
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 9.1.2 Motorola 6800 mode Table 16. Dynamic characteristics: LCD controller in Motorola 6800 mode CL = 25 pF, Tamb = 40 C to +85 C, unless otherwise specified; VDD(IO) = 1.8 V and 3.3 V (SUP8).
PAGE 47
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 9.1.3 Serial mode Table 17. Dynamic characteristics: LCD controller serial mode CL = 25 pF, Tamb = 40 C to +85 C, unless otherwise specified; VDD(IO) = 1.8 V and 3.3 V (SUP8).
PAGE 48
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 9.2 SRAM controller Table 18. Dynamic characteristics: static external memory interface CL = 25 pF, Tamb = 40 C to +85 C, unless otherwise specified; VDD(IO) = 1.8 V and 3.3 V (SUP8). Symbol Parameter Conditions Min Typ Max Unit 1.
PAGE 49
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers [4] One HCLK cycle delay added when SYSCREG_MPMC_WAITREAD_DELAYx register bit 5 = 1. [5] WAITRD must  to WAITOEN for there to be any delay between CS active and BLS active. The maximum delay is limited to (WAITRD * HCLK). [6] There is one less HCLK cycle when SYSCREG_MPMC_WAITREAD_DELAYx bit 5 = 1. [7] The MPMC will ensure a minimum of one HCLK for this parameter. [8] This formula applies when WAITWR is  WAITWEN.
PAGE 50
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers EBI_NSTCS_X tCSLAV EBI_A_[15:0] tBLSHANV tCSLDV tWEHANV EBI_D_[15:0] tWELWEH tCSLWEL tWEHDNV tWELDV tBLSHDNV EBI_NWE tBLSLBLSH tCSLBLSL EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 002aae162 Fig 15. External memory write access to static memory LPC3130_3131 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 May 2012 © NXP B.V. 2012. All rights reserved.
PAGE 51
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 9.3 SDRAM controller Table 19. Dynamic characteristics of SDR SDRAM memory interface Tamb = 40 C to +85 C, unless otherwise specified; VDD(IO) = 1.8 V and 3.3 V (SUP8).[1][2][3] Symbol Parameter Conditions [4] Min Typical Max Unit - 80 90 MHz foper operating frequency tCLCX clock LOW time - 5.55 - ns tCHCX clock HIGH time - 5.55 - ns - - 3.
PAGE 52
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers TCLCL tCLCX tCHCX EBI_CLKOUT td(o) EBI_NRAS_BLOUT EBI_NCAS_BLOUT EBI_NWE EBI_CKE EBI_NDYCS th(o) READ NOP NOP NOP td(o) READ NOP NOP th(o) EBI_DQMx th(A) EBI_A_[15:2] BANK, COLUMN tsu(D) th(D) EBI_D_[15:0] DATA n CAS LATENCY = 2 DATA n+2 DATA n+1 DATA n+3 002aae121 EBI_CKE is HIGH. Fig 16.
PAGE 53
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors LPC3130_3131 Product data sheet TCLCL tCLCX tCHCX EBI_CLKOUT td(o) th(o) EBI_CKE td
PAGE 54
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 9.4 NAND flash memory controller Table 20. Dynamic characteristics of the NAND flash memory controller Tamb = 40 C to +85 C, unless otherwise specified.
PAGE 55
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 9.5 Crystal oscillator Table 21: Dynamic characteristics: crystal oscillator Symbol Parameter fosc Conditions Min Typ Max Unit oscillator frequency 10 12 25 MHz clk clock duty cycle 45 50 55 % Cxtal crystal capacitance input; on pin FFAST_IN - - 2 pF output; on pin FFAST_OUT - - 0.74 pF tstartup start-up time - 500 - s Pdrive drive power 100 - 500 W 9.6 SPI Table 22.
PAGE 56
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers TSPICYC tSPICLKH tSPICLKL SCK (CPOL = 0) SCK (CPOL = 1) tSPIOH tSPIQV MOSI DATA VALID DATA VALID tSPIDSU MISO DATA VALID tSPIDH DATA VALID 002aad987 Fig 20. SPI master timing (CPHA = 0) TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH SCK (CPOL = 0) SCK (CPOL = 1) MOSI DATA VALID DATA VALID tSPIOH tSPIQV MISO DATA VALID DATA VALID 002aad988 Fig 21.
PAGE 57
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers TSPICYC tSPICLKH tSPICLKL SCK (CPOL = 0) SCK (CPOL = 1) tSPIDSU MOSI DATA VALID tSPIDH DATA VALID tSPIQV MISO DATA VALID tSPIOH DATA VALID 002aad989 Fig 22. LPC3130_3131 Product data sheet SPI slave timing (CPHA = 0) All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 May 2012 © NXP B.V. 2012. All rights reserved.
PAGE 58
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 9.6.1 Texas Instruments synchronous serial mode (SSI mode) Table 23. Dynamic characteristic: SPI interface (SSI mode) Tamb = 40 C to +85 C; VDD(IO) (SUP3) over specified ranges.
PAGE 59
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors LPC3130_3131 Product data sheet 10. Application information Table 25.
PAGE 60
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 11. Marking Table 26. LPC3130_3131 Product data sheet LPC3130/3131 Marking Line Marking Description A LPC3130/3131 BASIC_TYPE All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 May 2012 © NXP B.V. 2012. All rights reserved.
PAGE 61
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 12.
PAGE 62
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 13. Abbreviations Table 27.
PAGE 63
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers Table 27.
PAGE 64
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 14. Revision history Table 28: Revision history Document ID Release date Data sheet status Change notice Supersedes LPC3130_31 v.2 20120529 Product data sheet - LPC3130_3131 v.1 Modifications: LPC3130_3131 v.1 LPC3130_3131 Product data sheet • • • • • • • • • • • • • • • Updated Table 18 table notes. Updated Table 12 TBDs. Reset state of JTAG pins and GPIO0, GPIO1, and GPIO2 pins updated in Table 4.
PAGE 65
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
PAGE 66
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
PAGE 67
LPC3130/3131 NXP Semiconductors Low-cost, low-power ARM926EJ-S microcontrollers 17. Contents 1 2 2.1 3 4 5 5.1 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 6.23 6.24 6.25 6.26 6.26.1 6.26.2 6.26.3 6.27 6.28 6.29 6.30 7 8 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . .